SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.5.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus/I2C Target control mode), then the DS160PR410-Q1 is configured through a standard I2C or SMBus interface that may operate up to 400kHz. The target address of the DS160PR410-Q1 is determined by the pin strap settings on the ADDR1 and ADDR0 pins. The sixteen possible target addresses for each channel bank of the DS160PR410-Q1 are provided in Table 6-5. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3V supply with a pull-up resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

Table 6-5 SMBUS/I2C Target Address Settings
ADDR1 ADDR0 7-bit Target Address
L0 L0 0x18
L0 L1 0x1A
L0 L2 0x1C
L0 L3 0x1E
L1 L0 0x20
L1 L1 0x22
L1 L2 0x24
L1 L3 0x26
L2 L0 0x28
L2 L1 0x2A
L2 L2 0x2C
L2 L3 0x2E
L3 L0 0x30
L3 L1 0x32
L3 L2 0x34
L3 L3 0x36
X L4 Reserved

The DS160PR410-Q1 has two types of registers:

  • Shared Registers: these registers can be accessed at any time and are used for device-level configuration, status read back, control, or to read back the device ID information.
  • Channel Registers: these registers are used to control and configure specific features for each individual channel. All channels have the same register set and can be configured independent of each other or configured as a group through broadcast writes to Bank 0 or Bank 1.

The DS160PR410-Q1 features four channels.

Channel Registers Base Address Channel Access
0x00 Channel 0 registers
0x20 Channel 1 registers
0x40 Channel 2 registers
0x60 Channel 3 registers
0x80

Broadcast write channel Bank 0 registers,

read channel 0 registers
0xA0

Broadcast write channel 0-1 registers,

read channel 0 registers
0xC0

Broadcast write channel 2-3 registers,

read channel 2 registers
0xE0 Channels 0-3 Share registers