SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1.3 Application Curves

The DS160PR410-Q1 is a linear redriver that can be used to extend channel reach of a PCIe link. Normally, PCIe-compliant Tx and Rx are equipped with signal-conditioning functions and can handle channel losses of up to 28dB at 8GHz. With the DS160PR410-Q1, the total channel loss between a PCIe root complex and an end point can be extended by up to 12dB at 8GHz.

DS160PR410-Q1 Illustration of equalization by the DS160PR410-Q1Figure 7-4 Illustration of equalization by the DS160PR410-Q1

To demonstrate the reach extension capability of the DS160PR410-Q1, a setup is constructed where a GPU card is used as a PCIe root complex sending PCIe 4.0 compliance patterns as illustrated in Figure 7-4. The output of the GPU card is captured through a PCIe compliance baseboard (CBB). Additional loss is inserted by a SMA loss board. The DS160PR410-Q1 is removing jitter to open the eye diagrams closed by added jitter from board loss. Table 7-1 shows eye opening information.

Table 7-1 PCIe 4.0 Reach Extension using the DS160PR410-Q1
Setup GPU output eye through CBB Eye after loss board (redriver input) Redriver output eye

9 inch loss board (5dB)

Redriver EQ = 17

Eye width 16.4ps

Eye height 145mV

 closed

Eye width 41.3ps

Eye height 388mV

24 inch loss board (12.5dB)

Redriver EQ = 19

Eye width 20.2ps

Eye height 161mV