SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.9 Typical Jitter Characteristics

Figure 5-3 and Figure 5-4 show eye diagrams at 20Gbps that compare jitter through calibration traces (left), and jitter through DS160PR410-Q1 (right) at TI evaluation boards with minimal channels. The eye diagrams illustrate that DS160PR410-Q1 adds very little random jitter (RJ) - below instrumentation acuracy. Similar total jitter through calibration trace and DUT can be attributed to the residual equalization at EQ = 0 cleaning up DJ for input loss.

DS160PR410-Q1 Through Baseline Calibration Trace Setup for 16Gbps Figure 5-3 Through Baseline Calibration Trace Setup for 16Gbps
DS160PR410-Q1 Through DS160PR410-Q1 for 16Gbps Figure 5-4 Through DS160PR410-Q1 for 16Gbps