SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

DS160PR410-Q1 RGF Package, 40-Pin VQFN (Top View) Figure 4-1 RGF Package, 40-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
Control Interface
READ_ENn 14 I, 3.3V LVCMOS In SMBus/I2C Controller mode:
After device power up, when the pin is low, this initiates the SMBus / I2C Controller mode EEPROM read function. When EEPROM read is complete (indicated by assertion of DONEn low), this pin can be held low for normal device operation. During the EEPROM load process the device’s signal path is disabled.
In SMBus/I2C Target and Pin modes:
In these modes the pin is not used. The pin can be left floating. The pin has internal 1MΩ weak pull-down resistor.
EQ0 / ADDR0 15 I, 5-level In Pin mode:
Sets receiver linear equalization (CTLE) boost provided in Table 6-1. These pins are sampled at device power-up only.
In SMBus/I2C mode:
Sets SMBus / I2C target address as provided in Table 6-5. These pins are sampled at device power-up only.
EQ1 / ADDR1 16 I, 5-level
MODE 17 I, 5-level Sets device control configuration modes. 5-level IO pin as provided in Table 6-4. The pin can be exercised at device power up or in normal operation mode.
L0: Pin mode – device control configuration is done solely by strap pins.
L1: SMBus/I2C Controller mode – device control configuration is read from external EEPROM. When the DS160PR410-Q1 has finished reading from the EEPROM successfully, the chip drives the DONEn pin LOW. SMBus/I2C target function is available in this mode before, during or after EEPROM reading. Note: during EEPROM reading if the external SMBus/I2C controller wants to access DS160PR410-Q1 registers it must support arbitration.
L2: SMBus/I2C Target mode – device control configuration is done by an external SMBus/I2C controller.
L3 and L4 (Float): RESERVED – TI internal test modes.
RX_DET / SCL 18 I, 5-level / I/O, 3.3V LVCMOS, open drain In Pin mode:
Sets receiver detect state machine options as provided in Table 6-3. The pin is sampled at device power-up only.
In SMBus/I2C mode:
3.3V SMBus/I2C clock. External 1kΩ to 5kΩ pullup resistor is required as per SMBus / I2C interface standard.
GAIN / SDA 19 I, 5-level / I/O, 3.3V LVCMOS, open drain In Pin mode:
Flat gain (DC and AC) from the input to the output of the device. The pin is sampled at device power-up only.
In SMBus/I2C mode:
3.3V SMBus/I2C data. External 1kΩ to 5kΩ pullup resistor is required as per SMBus / I2C interface standard.
SEL 34 I, 3.3V LVCMOS The pin selects the cross-point mux paths. Active in all device control modes. 59kΩ internal pull-down. Note: the pin also triggers PCIe RX detect state machine when toggled. For PCIe redriver use cases without mux function leave the pin unconnected. Low: straight data path – RX[0/1/2/3][P/N] connected to TX[0/1/2/3][P/N] through the redriver. High: cross data path – RX[0/1/2/3][P/N] connected to TX[1/0/3/2][P/N] through the redriver.
PD 38 I, 3.3V LVCMOS 2-level logic controlling the operating state of the redriver. Active in all device control modes. The pin has internal 1MΩ weak pull-down resistor. The pin triggers PCIe Rx detect state machine when toggled.
High: power down
Low: power up, normal operation
DONEn 39 O, 3.3V open drain In SMBus/I2C Controller mode:
Indicates the completion of a valid EEPROM register load operation. External pullup resistor such as 4.7kΩ required for operation.
High: External EEPROM load failed or incomplete
Low: External EEPROM load successful and complete
In SMBus/I2C Target/Pin mode:
This output is High-Z. The pin can be left floating.
Data Interface
TX3N 1 O Inverting pin for 100Ω differential driver output. Channel 3.
TX3P 2 O Non-inverting pin for 100Ω differential driver output. Channel 3.
TX2N 4 O Inverting pin for 100Ω differential driver output. Channel 2.
TX2P 5 O Non-inverting pin for 100Ω differential driver output. Channel 2.
TX1N 8 O Inverting pin for 100Ω differential driver output. Channel 1.
TX1P 9 O Non-inverting pin for 100Ω differential driver output. Channel 1.
TX0N 11 O Inverting pin for 100Ω differential driver output. Channel 0.
TX0P 12 O Non-inverting pin for 100Ω differential driver output Channel 0.
RX0P 21 I Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX0N 22 I Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 0.
RX1P 24 I Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX1N 25 I Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 1.
RX2P 28 I Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX2N 29 I Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 2.
RX3P 31 I Non-inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
RX3N 32 I Inverting differential inputs to the equalizer. Integrated 50Ω termination resistor from the pin to internal CM bias voltage. Channel 3.
Power, other
GND EP, 3, 10, 13, 20, 23, 30, 33, 40 G Ground reference for the device.
EP: the Exposed Pad at the bottom of the QFN package. This is used as the GND return for the device. The EP must be connected to one or more ground planes through the low resistance path. A via array provides a low impedance path to GND. The EP also improves thermal dissipation.
VCC 6, 7, 26, 27 P Power supply pins. VCC = 3.3V ±10%. The VCC pins on this device must be connected through a low-resistance path to the board VCC plane. Install a decoupling capacitor to GND near each VCC pin.
NC 35, 36, 37 - No connect. Leave floating.
(1) I = input, O = output, P = power, G = ground