SNLS729 September   2025 DS160PR410-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linear Equalization
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Receiver Detect State Machine
      4. 6.3.4 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active PCIe Mode
      2. 6.4.2 Linear Equalizer (Buffer) Mode
      3. 6.4.3 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin Mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I 2 C Controller Mode Configuration (EEPROM Self Load)
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 x4 Lane Configuration
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.1.1 Design Requirements

As with any high-speed design, there are many factors which influence the overall performance. The following list indicates critical areas for consideration during design.

  • Use 85Ω impedance traces when interfacing with PCIe CEM connectors. Length matching on the P and N traces must be done on the single-end segments of the differential pair.
  • Use a uniform trace width and trace spacing for differential pairs.
  • Place AC-coupling capacitors near the receiver end of each channel segment to minimize reflections.
  • For PCIe AC-coupling capacitors of 220nF are recommended. Set the maximum body size to 0402 and add a cutout void on the GND plane below the landing pad of the capacitor to reduce parasitic capacitance to GND.
  • Back-drill connector vias and signal vias to minimize stub length.
  • Use reference plane vias to make a low inductance path for the return current.