SNLS787 September   2025 TDP2004-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 RX Equalization Control Settings
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I2C Controller Mode Configuration (EEPROM Self Load)
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP2.1 Main Link Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 USB-C Cross Point Mux with Signal Conditioner
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

6.5.3 SMBus/I2C Controller Mode Configuration (EEPROM Self Load)

The TDP2004-Q1 can also be configured by reading from EEPROM. To enter into this mode MODE pin must be set to L1. The EEPROM load operation only happens once after the initial powerup of the device. If the TDP2004-Q1 is configured for SMBus Controller mode, the device remains in the SMBus IDLE state until the READ_ENn pin is asserted to LOW. After the READ_ENn pin is driven LOW, theTDP2004-Q1 becomes an SMBus Controller and attempts to self-configure by reading the device settings stored in an external EEPROM (SMBus 8-bit address 0xA0). When the TDP2004-Q1 has finished reading from the EEPROM successfully, the device drives the DONEn pin LOW. SMBus/I2C Target operation is available in this mode before, during, or after EEPROM reading. Note: during EEPROM reading, if the external SMBus/I2C Controller wants to access TDP2004-Q1 registers, the external controller must support arbitration.

When designing a system for using the external EEPROM, the user must follow these specific guidelines:

  • EEPROM size of 2Kb (256 × 8-bit) is recommended.
  • Set MODE = L1, configure for SMBus Controller mode.
  • The external EEPROM device address byte must be 0xA0 and capable of 400kHz operation at 3.3V supply
  • In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3V supply with a pullup resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

Multiple TDP2004-Q1 can be cascaded to read from single EEPROM. Tie the READ_ENn pin of the first device low (GND) to automatically initiate EEPROM read at power up. DONEn of the first device can be fed into READ_ENn of the next device with 4.7kΩ pullup resistors. Leave the DONEn pin of the final device floating, or connect the pin to a micro-controller input to monitor the completion of the final EEPROM read.