SNLS787 September   2025 TDP2004-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 RX Equalization Control Settings
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I2C Controller Mode Configuration (EEPROM Self Load)
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP2.1 Main Link Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 USB-C Cross Point Mux with Signal Conditioner
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

6.3.1 RX Equalization Control Settings

The TDP2004-Q1 receivers feature a continuous-time linear equalizer (CTLE) that applies high-frequency boost and low-frequency attenuation to help equalize the frequency-dependent insertion loss effects of the passive channel. The receivers implement two stage linear equalizer for wide range of equalization capability. The equalizer stages also provide flexibility to make subtle modifications of mid-frequency boost for best EQ gain profile match with wide range of channel media characteristics. The EQ profile control feature is only available in SMBus/I2C mode. In Pin mode the settings are optimized for FR4 traces.

Table 6-1 provides available equalization boost at 20Gbps (10GHz Nyquist frequency) through EQ control pins or SMBus/I2C registers. In Pin Control mode EQ1 and EQ0 pins set equalization boost for channels 0-3. In I2C mode individual channels can be independently programmed for EQ boost.

Table 6-1 Equalization Control Settings
EQUALIZATION SETTINGTYPICAL EQ BOOST (dB)
EQ INDEXPin modeSMBus/I2C Modeat 10GHz
EQ1EQ0eq_stage1_3:0eq_stage2_2:0eq_profile_3:0eq_stage1_bypass
0L0L000015.0
1L0L110017.0
2L0L230018.0
5L1L0001010.0
6L1L1101010.5
7L1L2201011.5
8L1L3303012.0
9L1L4403013.0
10L2L0517013.5
11L2L1617014.0
12L2L2817015.5
13L2L31017016.0
14L2L410215016.5
15L3L011315017.5
16L3L112415018.5
17L3L213515019.0
18L3L314615020.0
19L3L415715020.5