SNLS787 September   2025 TDP2004-Q1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Pin Configuration and Functions
  6. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 DC Electrical Characteristics
    6. 5.6 High Speed Electrical Characteristics
    7. 5.7 SMBUS/I2C Timing Charateristics
    8. 5.8 Typical Characteristics
    9. 5.9 Typical Jitter Characteristics
  7. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 RX Equalization Control Settings
      2. 6.3.2 Flat-Gain
      3. 6.3.3 Cross Point
    4. 6.4 Device Functional Modes
      1. 6.4.1 Active Mode
      2. 6.4.2 Standby Mode
    5. 6.5 Programming
      1. 6.5.1 Pin mode
        1. 6.5.1.1 Five-Level Control Inputs
      2. 6.5.2 SMBUS/I2C Register Control Interface
        1. 6.5.2.1 Shared Registers
        2. 6.5.2.2 Channel Registers
      3. 6.5.3 SMBus/I2C Controller Mode Configuration (EEPROM Self Load)
  8. 7Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 DP2.1 Main Link Signal Conditioning
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
      2. 7.2.2 USB-C Cross Point Mux with Signal Conditioner
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9Mechanical, Packaging, and Orderable Information

6.5.2 SMBUS/I2C Register Control Interface

If MODE = L2 (SMBus/I2C Target control mode), then the TDP2004-Q1 is configured through a standard I2C or SMBus interface that can operate up to 400kHz. The Target address of the TDP2004-Q1 is determined by the pin strap settings on the ADDR1 and ADDR0 pins. The sixteen possible Target addresses for channels 0-3 are provided in Table 6-4. In SMBus/I2C modes the SCL and SDA pins must be pulled up to a 3.3V supply with a pullup resistor. The value of the resistor depends on total bus capacitance. 4.7kΩ is a good first approximation for a bus capacitance of 10pF.

Table 6-4 SMBUS/I2C Target Address Settings
ADDR1ADDR07-bit Target Address Channels 0-3
L0L00x18
L0L10x1A
L0L20x1C
L0L30x1E
L0L4Reserved
L1L00x20
L1L10x22
L1L20x24
L1L30x26
L1L4Reserved
L2L00x28
L2L10x2A
L2L20x2C
L2L30x2E
L2L4Reserved
L3L00x30
L3L10x32
L3L20x34
L3L30x36
L3L4Reserved

The TDP2004-Q1 has two types of registers:

  • Shared Registers: these registers can be accessed at any time and are used for device-level configuration, status read back, control, or to read back the device ID information.
  • Channel Registers: these registers are used to control and configure specific features for each individual channel. All channels have the same register set and can be configured independent of each other or configured as a group through broadcast writes to Channels 0-3.
Table 6-5 Channel Register Access
Channel Registers Base AddressChannel 0-3 Access
0x00Channel 0 registers
0x20Channel 1 registers
0x40Channel 2 registers
0x60Channel 3 registers
0x80Broadcast write channel 0-3 registers, read channel 0 registers
0xA0Broadcast write channel 0-1 registers, read channel 0 registers
0xC0Broadcast write channel 2-3 registers, read channel 2 registers
0xE0Channel 0-3 share registers