The DP83826A is a single-port physical layer transceiver designed to meet stringent Industrial fieldbus applications' needs and offers very low latency, deterministic variation in latency (across reset, power cycle), fixed phase between XI and TX_CLK, low power, and configuration using hardware bootstraps to achieve fast link up. The device supports the standard MII and RMII (Master mode and Slave mode) for direct connection to the media access controller (MAC). Its dedicated CLKOUT pin can be used to clock other modules on the system. In addition, the PWRDN pin controls the DP83826A link up from power-on-reset (POR) and helps with design of asynchronous power-up of the DP83826A and host system-on-a-chip (SoC) or field-programmable-gate-array (FPGA) controller.