Simulation models were built using ANSYS finite element analysis (FEA) software in order to compare thermal performance (i.e., R_θJC/P) of different surface-mount packages. Illustrations of four models including QFN 8x8, QFN 12x12, TOLL, and D²PAK packages are shown in Figure 4-1. The former two QFN packages are implemented for TI’s 600-V GaN power stage products while the latter two are used by competitors for their commercially released 600-V GaN and 650-V SiC discrete devices respectively. Each surface-mount device is placed on the center of a 4-layer PCB in 40-mm x 40-mm surface area and 1.58-mm thickness.

An example cross-sectional view of the generated model with a detailed description on the multilayer PCB structure is displayed in Figure 4-2. Most building elements including thermal via patten design (Figure 4-3) are the same for all built models except two items: PCB top Cu layer design and total numbers of thermal vias, which were adjusted to fit for the thermal pad area of each package for the purpose of a fair thermal performance comparison among different packages. Please note that the top Cu pad for heat spreading and the corresponding thermal via pattern/number can be further optimized for specific applications. Table 4-1 summarizes the key dimensional and thermal information for major modelling components.