Some ADCs load the signal source with a sample and hold capacitor. The capacitor can be discharged prior to being connected to the signal source. If the LMP860x-Q1 are driving such ADCs, the sudden current that is delivered when the sampling occurs can disturb the output signal. This effect is simulated with the circuit shown in Figure 6-4 where the output is to a capacitor that is driven by a rail-to-rail square wave.

Figure 6-4 Driving Switched Capacitive Load

This circuit simulates the switched connection of a discharged capacitor to the LMP860x-Q1 output. The resulting V_OUT disturbance signals are shown in Figure 6-5 and Figure 6-6.

Figure 6-5 Capacitive Load Response at 3.3V

Figure 6-6 Capacitive Load Response at 5.0V

These figures can be used to estimate the disturbance that is caused when driving a switched capacitive load. To minimize the error signal introduced by the sampling that occurs on the ADC input, place an additional RC filter between the LMP860x-Q1 and the ADC, as illustrated in Figure 6-7.

Figure 6-7 Reduce Error When Driving ADCs

The external capacitor absorbs the charge that flows when the ADC sampling capacitor is connected. The external capacitor must be much larger than the sample-and-hold capacitor at the input of the ADC, and the RC time constant of the external filter must be such that the speed of the system is not affected.