SNOSAV4C April   2008  – August 2026 LM7332

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
    7. 5.7 Old vs. New Die Comparison
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Device Functional Modes
      1. 6.3.1 Driving Capacitive Loads
    4. 6.4 Electrical Overstress
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Output Short Circuit Current and Dissipation Issues
  9. 8 Device and Documentation Support
    1. 8.1 Support Resources
    2. 8.2 Trademarks
    3. 8.3 Electrostatic Discharge Caution
    4. 8.4 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

9 Revision History

Changes from Revision B (December 2015) to Revision C (August 2026)

  • Updated Wide Supply Voltage Range minimum from 2.5V to 2.7VGo
  • Removed High Output Current featureGo
  • Updated GBWP from 21MHz to 24MHzGo
  • Updated Slew Rate from 15.2V/μs to 35V/μsGo
  • Updated Total Supply Current from 2mA to 2.7mAGo
  • Updated Supply voltage (VS = V+ – V−) from 35V to 33VGo
  • Updated Voltage at input/output pins minimum from V+ + 0.3V to V− − 0.5V and maximum from V− − 0.3V to V+ + 0.5V Go
  • Added Charged-device model RatingsGo
  • Updated Junction-to-ambient thermal resistance for DGK (VSSOP) package from 161.1°C/W to 169.6°C/WGo
  • Updated Junction-to-ambient thermal resistance for D (SOIC) package from 109.1°C/W to 124.0°C/WGo
  • Updated Junction-to-case (top) thermal resistance for DGK (VSSOP) package from 55°C/W to 61.6°C/WGo
  • Updated Junction-to-case (top) thermal resistance for D (SOIC) package from 55.8°C/W to 67.3°C/WGo
  • Updated Junction-to-board thermal resistance for DGK (VSSOP) package from 80.5°C/W to 91.2°C/WGo
  • Updated Junction-to-board thermal resistance for D (SOIC) package from49.2°C/W to 68.4°C/WGo
  • Updated Junction-to-top characterization parameter for DGK (VSSOP) package from 5.5°C/W to 9.0°C/WGo
  • Updated Junction-to-top characterization parameter for D (SOIC) package from 10.7°C/W to 19.9°C/WGo
  • Updated Junction-to-board characterization parameter for DGK (VSSOP) package from 79.2°C/W to 89.7°C/WGo
  • Updated Junction-to-board characterization parameter for D (SOIC) package from 48.7°C/W to 67.6°C/WGo
  • Updated Wide Supply Voltage Range minimum from 2.5V to 2.7VGo
  • Updated Input offset voltage typical value from ±1.6mV to ±0.35Go
  • Updated Input offset voltage temperature drift typical value from ±2µV/°C to ±2.5µV/°CGo
  • Updated Input bias current typical value from ±1µA to 0.4µAGo
  • Updated Input offset current typical value from 20nA to 7nAGo
  • Updated Input common-mode voltage range minimum value from 5.1V to (V−) − 0.1Go
  • Updated Input common-mode voltage range minimum value from −5.1V to (V+) + 0.1Go
  • Removed Input common-mode voltage range typical value Go
  • Updated all Output swing high and Output swing low typical values to 50mV (from either rail)Go
  • Updated CMRR specification as per New Die CharacteristicsGo
  • Updated Total supply current typical value from 1.5mA to 2.7mA and maximum values for TA= 25°C from 2.4mA to 3.86mA and for TA = –40°C to +125°C from 2.6mA to 4.46mAGo
  • Updated Slew rate typical value from 13.2V/μs to 35V/μsGo
  • Updated Close-loop output resistance from 3Ω to 1ΩGo
  • Updated Unity-gain frequency 7.9MHz to 11MHzGo
  • Updated Gain bandwidth product from 19.9MHz to 24MHzGo
  • Updated Total harmonic distortion + noise from -87dB to -113dBGo
  • Updated Crosstalk rejection from 68dB to 120dBGo
  • Updated plots as per New Die CharacteristicsGo
  • Added Old vs. New Die Comparison sectionGo
  • Removed Output Voltage Swing Close to V− sectionGo
  • Added Electrical Overstress sectionGo

Changes from Revision A (March 2013) to Revision B (December 2015)

  • Added Device Information, ESD Ratings and Thermal Information table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go

Changes from Revision * (March 2013) to Revision A (March 2013)