SNOSB24C October   2008  – November 2025 LM5576-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Shutdown / Standby
      2. 6.3.2 Soft Start
      3. 6.3.3 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 High Voltage Start-Up Regulator
      2. 6.4.2 Oscillator and Sync Capability
      3. 6.4.3 Error Amplifier and PWM Comparator
      4. 6.4.4 Ramp Generator
      5. 6.4.5 Maximum Duty Cycle / Input Dropout Voltage
      6. 6.4.6 Boost Pin
      7. 6.4.7 Current Limit
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bias Power Dissipation Reduction
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  External Components
        3. 7.2.2.3  R3 (RT)
        4. 7.2.2.4  L1
        5. 7.2.2.5  C3 (CRAMP)
        6. 7.2.2.6  C9, C10
        7. 7.2.2.7  D1
        8. 7.2.2.8  C1, C2
        9. 7.2.2.9  C8
        10. 7.2.2.10 C7
        11. 7.2.2.11 C4
        12. 7.2.2.12 R5, R6
        13. 7.2.2.13 R1, R2, C12
        14. 7.2.2.14 R7, C11
        15. 7.2.2.15 R4, C5, C6
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Power Dissipation
      4. 7.4.4 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.4 Ramp Generator

The ramp signal used in the pulse width modulator for current mode control is typically derived directly from the buck switch current. This switch current corresponds to the positive slope portion of the output inductor current. Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and provides inherent input voltage feed-forward compensation. The disadvantage of using the buck switch current signal for PWM control is the large leading edge spike due to circuit parasitics that must be filtered or blanked. Also, the current measurement can introduce significant propagation delays. The filtering, blanking time, and propagation delay limit the minimum achievable pulse width. In applications where the input voltage can be relatively large in comparison to the output voltage, controlling small pulse widths and duty cycles is necessary for regulation. The LM5576-Q1 uses a unique ramp generator, which does not actually measure the buck switch current but rather reconstructs the signal. Reconstructing or emulating the inductor current provides a ramp signal to the PWM comparator that is free of leading edge spikes and measurement or filtering delays. The current reconstruction is comprised of two elements: a sample and hold DC level and an emulated current ramp.

LM5576-Q1 Composition of Current Sense SignalFigure 6-5 Composition of Current Sense Signal

The sample and hold DC level shown in Figure 6-5 is derived from a measurement of the re-circulating Schottky diode anode current. The re-circulating diode anode must be connected to the IS pin. The diode current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch. The diode current sensing and sample and hold provide the DC level of the reconstructed current signal. The positive slope inductor current ramp is emulated by an external capacitor connected from the RAMP pin to AGND and an internal voltage controlled current source. The ramp current source that emulates the inductor current is a function of the VIN and VOUT voltages per Equation 2.

Equation 2. IRAMP = (5 µ × (VIN – VOUT)) + 25µA

Proper selection of the RAMP capacitor depends upon the selected value of the output inductor. Use Equation 3 to select a value of CRAMP.

Equation 3. CRAMP = L × 10–5

where

  • L is the value of the output inductor in Henrys

With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC level sample and hold (0.5V/A). The CRAMP capacitor must be placed very close to the device and connected directly to the pins of the IC (RAMP and AGND).

For duty cycles greater than 50%, peak current mode control circuits are subject to sub-harmonic oscillation. Sub-harmonic oscillation is normally characterized by observing alternating wide and narrow pulses at the switch node. Adding a fixed slope voltage ramp (slope compensation) to the current sense signal prevents this oscillation. The 25µA of offset current provided from the emulated current source adds some fixed slope to the ramp signal. In some high output voltage, high duty cycle applications, additional slope can be required. In these applications, a pullup resistor can be added between the VCC and RAMP pins to increase the ramp slope compensation.

For VOUT > 7.5V:

Calculate optimal slope current, IOS = VOUT × 5µA/V.

For example, at VOUT = 10V, IOS = 50µA.

Use Equation 4 to install a resistor from the RAMP pin to VCC:

Equation 4. RRAMP = VCC / (IOS – 25µA)
LM5576-Q1 RRAMP to VCC for VOUT > 7.5VFigure 6-6 RRAMP to VCC for VOUT > 7.5V

Note that the emulated ramp signal on CRAMP is applied to the current limit comparator as described in the Section 6.4.7. Increasing the ramp slope results in lower current limit threshold. This result can lower the output current capability of the part to less than 3A in some conditions. The resulting current limit threshold can be calculated by Equation 5.

Equation 5. LM5576-Q1

where

  • VCL = 2.1V
  • gm = 5µA/V
  • Ioffset = 25µA
  • A x Rs = 0.5V/A
  • VCC = 7V
  • T = switching period
  • D = duty cycle (approximately VOUT / VIN)
  • L = inductor value
  • CRAMP = ramp capacitor value
  • RRAMP = ramp resistor value

If the recommended CRAMP and RRAMP values are used, then Equation 6 can calculate the current limit threshold:

Equation 6. LM5576-Q1