SNOSB24C October   2008  – November 2025 LM5576-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Shutdown / Standby
      2. 6.3.2 Soft Start
      3. 6.3.3 Thermal Protection
    4. 6.4 Device Functional Modes
      1. 6.4.1 High Voltage Start-Up Regulator
      2. 6.4.2 Oscillator and Sync Capability
      3. 6.4.3 Error Amplifier and PWM Comparator
      4. 6.4.4 Ramp Generator
      5. 6.4.5 Maximum Duty Cycle / Input Dropout Voltage
      6. 6.4.6 Boost Pin
      7. 6.4.7 Current Limit
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Bias Power Dissipation Reduction
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1  Custom Design With WEBENCH® Tools
        2. 7.2.2.2  External Components
        3. 7.2.2.3  R3 (RT)
        4. 7.2.2.4  L1
        5. 7.2.2.5  C3 (CRAMP)
        6. 7.2.2.6  C9, C10
        7. 7.2.2.7  D1
        8. 7.2.2.8  C1, C2
        9. 7.2.2.9  C8
        10. 7.2.2.10 C7
        11. 7.2.2.11 C4
        12. 7.2.2.12 R5, R6
        13. 7.2.2.13 R1, R2, C12
        14. 7.2.2.14 R7, C11
        15. 7.2.2.15 R4, C5, C6
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Power Dissipation
      4. 7.4.4 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Custom Design With WEBENCH® Tools
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.2.2.15 R4, C5, C6

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One advantage of current mode control is the ability to close the loop with only two feedback components, R4 and C5. The overall loop gain is the product of the modulator gain and the error amplifier gain. Use Equation 17 to calculate the DC modulator gain of the LM5576-Q1.

Equation 17. DC Gain(MOD) = Gm(MOD) × RLOAD = 2 × RLOAD

The dominant low frequency pole of the modulator is determined by the load resistance (RLOAD,) and output capacitance (COUT). Use Equation 18 to calculate the corner frequency of this pole.

Equation 18. fp(MOD) = 1 / (2π RLOAD COUT)

For RLOAD = 5Ω and COUT = 177µF, then fp(MOD) = 180Hz

DC Gain(MOD) = 2 × 5 = 10 = 20dB

For the design example of Figure 7-3 the measured modulator gain vs. frequency characteristic is shown in Figure 7-5.

LM5576-Q1 Gain and Phase of Modulator R = 5Ω and C = 177µF LoadoutFigure 7-5 Gain and Phase of Modulator R = 5Ω and C = 177µF Loadout

Components R4 and C5 configure the error amplifier as a type II configuration that has a pole at DC and a zero at fZ = 1 / (2πR4C5). The error amplifier zero cancels the modulator pole, which leaves a single pole response at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 20kHz was selected. The compensation network zero (fZ) must be selected at least an order of magnitude less than the target crossover frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2π R4C5) to be less than 2kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely, decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was selected for 0.01µF and R4 was selected for 49.9kΩ. These values configure the compensation network zero at 320Hz. The error amp gain at frequencies greater than fZ is: R4 / R5, which is approximately 10 (20dB).

LM5576-Q1 Error Amplifier Gain and PhaseFigure 7-6 Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

LM5576-Q1 Overall Loop Gain and PhaseFigure 7-7 Overall Loop Gain and Phase

If a network analyzer is available, the modulator gain can be measured and the error amplifier gain can be configured for the desired loop transfer function. If a network analyzer is not available, the error amplifier compensation components can be designed with the guidelines given. Step load transient tests can be performed to verify acceptable performance. The step load goal is minimum overshoot with a damped response. C6 can be added to the compensation network to decrease noise susceptibility of the error amplifier. The value of C6 must be sufficiently small because the addition of this capacitor adds a pole in the error amplifier transfer function. This pole must be well beyond the loop crossover frequency. Use Equation 19 to calculate a good approximation of the location of the pole added by C6.

Equation 19. fp2 = fz × C5 / C6.