SNVSC52A December   2021  – October 2026 LP5864

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7.     14
    8. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Time-Multiplexing Matrix
      2. 7.3.2 Analog Dimming (Current Gain Control)
      3. 7.3.3 PWM Dimming
      4. 7.3.4 ON and OFF Control
      5. 7.3.5 Data Refresh Mode
      6. 7.3.6 Full Addressable SRAM
      7. 7.3.7 Protections and Diagnostics
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Interface Selection
      2. 7.5.2 I2C Interface
        1. 7.5.2.1 I2C Data Transactions
        2. 7.5.2.2 I2C Data Format
        3. 7.5.2.3 Multiple Devices Connection
      3. 7.5.3 SPI
        1. 7.5.3.1 SPI Data Transactions
        2. 7.5.3.2 SPI Data Format
        3. 7.5.3.3 Multiple Devices Connection
  9. 8 Register Maps
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Program Procedure
      5. 9.2.5 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.3.5 Data Refresh Mode

The LP5864 supports three data refresh modes: Mode 1, Mode 2, and Mode 3, by configuring 'Data_Ref_Mode' in Dev_initial register.

Mode 1: 8-bit PWM data without VSYNC command. Data is sent out for display instantly after received. With Mode 1, users can refresh the corresponding dots' data only instead of updating the whole SRAM. This refresh is called ‘on demand data refresh’, which can save the total data volume effectively. As shown in Figure 7-7, the red LED dots can be refreshed after sending the corresponding data while the others kept the same with last frame.

LP5864 On Demand Data Refresh - Mode 1Figure 7-7 On Demand Data Refresh - Mode 1

Mode 2: 8-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after receiving the VSYNC command.

Mode 3: 16-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after receiving the VSYNC command.

Frame control is implemented in Mode 2 and Mode 3. Instead of refreshing the output instantly after data is received (Mode 1), the device holds the data and refreshes the whole frame data by a fixed frame rate, fVSYNC. Typically, 24Hz, 50Hz, 60Hz, 120Hz or even higher frame rate is selected to achieve vivid animation effects. Whole SRAM Data Refresh is shown in Figure 7-8, a new frame is updated after receiving the VSYNC command.

LP5864 Whole SRAM Data Refresh Figure 7-8 Whole SRAM Data Refresh

Comparing with Mode 1, Mode 2 and Mode 3 provide a better synchronization when multiple LP5864 devices used together. A high-level pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame. Figure 7-9 shows the VSYNC connections and Figure 7-10 shows the timing requirements.

LP5864 Multiple Devices Sync Figure 7-9 Multiple Devices Sync
LP5864 VSYNC Timing Figure 7-10 VSYNC Timing

Table 7-4 summarizes the three data refresh modes.

Table 7-4 Data Refresh Mode
MODE TYPE PWM RESOLUTION PWM OUTPUT EXTERNAL VSYNC
Mode 1 8 bits Data update instantly No
Mode 2 8 bits Data update by frame Yes
Mode 3 16 bits