SNVSCQ1A March   2025  – August 2025 LP5816

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Dimming
      2. 7.3.2 PWM Dimming
      3. 7.3.3 Sloper
      4. 7.3.4 Protections
        1. 7.3.4.1 UVLO
        2. 7.3.4.2 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Initialization Mode
      2. 7.4.2 Standby and Normal Mode
      3. 7.4.3 Shutdown Mode
      4. 7.4.4 Thermal Shutdown Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Data Tansactions
      2. 7.5.2 I2C Data Format
      3. 7.5.3 Command Description
    6. 7.6 Register Maps
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Parameters
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Program Procedure
        2. 8.2.3.2 Programming Example
      4. 8.2.4 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.6 Register Maps

Table 7-6 Register Maps
AddressAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0hCHIP_ENRESERVEDCHIP_EN
1hDEV_CONFIG0RESERVEDMAX_CURRENT
2hDEV_CONFIG1RESERVEDOUT3_ENOUT2_ENOUT1_ENOUT0_EN
3hDEV_CONFIG2LED_FADE_TIMEOUT3_FADE_ENOUT2_FADE_ENOUT1_FADE_ENOUT0_FADE_EN
4hDEV_CONFIG3OUT3_EXP_ENOUT2_EXP_ENOUT1_EXP_ENOUT0_EXP_ENRESERVED
DhSHUTDOWN_CMDSHUTDOWN
EhRESET_CMDRESET
FhUPDATE_CMDUPDATE
13hFLAG_CLRRESERVEDTSD_CLRPOR_CLR
14hOUT0_DCOUT0_DC
15hOUT1_DCOUT1_DC
16hOUT2_DCOUT2_DC
17hOUT3_DCOUT3_DC
18hOUT0_MANUAL_PWMOUT0_MANUAL_PWM
19hOUT1_MANUAL_PWMOUT1_MANUAL_PWM
1AhOUT2_MANUAL_PWMOUT2_MANUAL_PWM
1BhOUT3_MANUAL_PWMOUT3_MANUAL_PWM
40hFLAGRESERVEDTSDPOR

Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.

Table 7-7 Register Maps Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

7.6.1 CHIP_EN (Address = 0h) [Reset = 00h]

CHIP_EN is shown in Figure 7-9 and described in Table 7-8.

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Figure 7-9 CHIP_EN
76543210
RESERVEDCHIP_EN
R-0hR/W-0h
Table 7-8 CHIP_EN Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h Reserved
0CHIP_ENR/W0h Device enable.
0x0 = Disable
0x1 = Enable

7.6.2 DEV_CONFIG0 (Address = 1h) [Reset = 00h]

DEV_CONFIG0 is shown in Figure 7-10 and described in Table 7-9.

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Figure 7-10 DEV_CONFIG0
76543210
RESERVEDMAX_CURRENT
R-0hR/W-0h
Table 7-9 DEV_CONFIG0 Field Descriptions
BitFieldTypeResetDescription
7-1RESERVEDR0h Reserved
0MAX_CURRENTR/W0h Max output current.
0x0 = 25.5mA
0x1 = 51mA

7.6.3 DEV_CONFIG1 (Address = 2h) [Reset = 00h]

DEV_CONFIG1 is shown in Figure 7-11 and described in Table 7-10.

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Figure 7-11 DEV_CONFIG1
76543210
RESERVEDOUT3_ENOUT2_ENOUT1_ENOUT0_EN
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-10 DEV_CONFIG1 Field Descriptions
BitFieldTypeResetDescription
7-4RESERVEDR0h Reserved
3OUT3_ENR/W0h OUT3 enable.
0x0 = Disable
0x1 = Enable
2OUT2_ENR/W0h OUT2 enable.
0x0 = Disable
0x1 = Enable
1OUT1_ENR/W0h OUT1 enable.
0x0 = Disable
0x1 = Enable
0OUT0_ENR/W0h OUT0 enable.
0x0 = Disable
0x1 = Enable

7.6.4 DEV_CONFIG2 (Address = 3h) [Reset = 00h]

DEV_CONFIG2 is shown in Figure 7-12 and described in Table 7-11.

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Figure 7-12 DEV_CONFIG2
76543210
LED_FADE_TIMEOUT3_FADE_ENOUT2_FADE_ENOUT1_FADE_ENOUT0_FADE_EN
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 7-11 DEV_CONFIG2 Field Descriptions
BitFieldTypeResetDescription
7-4LED_FADE_TIMER/W0h OUT fade sloper time.
0x0 = 0s
0x1 = 0.05s
0x2 = 0.10s
0x3 = 0.15s
0x4 = 0.20s
0x5 = 0.25s
0x6 = 0.30s
0x7 = 0.35s
0x8 = 0.40s
0x9 = 0.45s
0xA = 0.50s
0xB = 1.00s
0xC = 2.00s
0xD = 4.00s
0xE = 6.00s
0xF = 8.00s
3OUT3_FADE_ENR/W0h OUT3 fade in and out enable.
0x0 = Disable
0x1 = Enable
2OUT2_FADE_ENR/W0h OUT2 fade in and out enable.
0x0 = Disable
0x1 = Enable
1OUT1_FADE_ENR/W0h OUT1 fade in and out enable.
0x0 = Disable
0x1 = Enable
0OUT0_FADE_ENR/W0h OUT0 fade in and out enable.
0x0 = Disable
0x1 = Enable

7.6.5 DEV_CONFIG3 (Address = 4h) [Reset = 00h]

DEV_CONFIG3 is shown in Figure 7-13 and described in Table 7-12.

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Figure 7-13 DEV_CONFIG3
76543210
OUT3_EXP_ENOUT2_EXP_ENOUT1_EXP_ENOUT0_EXP_ENRESERVED
R/W-0hR/W-0hR/W-0hR/W-0hR-0h
Table 7-12 DEV_CONFIG3 Field Descriptions
BitFieldTypeResetDescription
7OUT3_EXP_ENR/W0h OUT3 exponential PWM dimming enable.
0x0 = Disable
0x1 = Enable
6OUT2_EXP_ENR/W0h OUT2 exponential PWM dimming enable.
0x0 = Disable
0x1 = Enable
5OUT1_EXP_ENR/W0h OUT1 exponential PWM dimming enable.
0x0 = Disable
0x1 = Enable
4OUT0_EXP_ENR/W0h OUT0 exponential PWM dimming enable.
0x0 = Disable
0x1 = Enable
3-0RESERVEDR0h Reserved

7.6.6 SHUTDOWN_CMD (Address = Dh) [Reset = 00h]

SHUTDOWN_CMD is shown in Figure 7-14 and described in Table 7-13.

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Figure 7-14 SHUTDOWN_CMD
76543210
SHUTDOWN
W-0h
Table 7-13 SHUTDOWN_CMD Field Descriptions
BitFieldTypeResetDescription
7-0SHUTDOWNW0h 0x33 = Enter shutdown mode

7.6.7 RESET_CMD (Address = Eh) [Reset = 00h]

RESET_CMD is shown in Figure 7-15 and described in Table 7-14.

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Figure 7-15 RESET_CMD
76543210
RESET
W-0h
Table 7-14 RESET_CMD Field Descriptions
BitFieldTypeResetDescription
7-0RESETW0h 0xCC = Reset all the registers to default value

7.6.8 UPDATE_CMD (Address = Fh) [Reset = 00h]

UPDATE_CMD is shown in Figure 7-16 and described in Table 7-15.

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Figure 7-16 UPDATE_CMD
76543210
UPDATE
W-0h
Table 7-15 UPDATE_CMD Field Descriptions
BitFieldTypeResetDescription
7-0UPDATEW0h 0x55 = Update all device configuration registers value

7.6.9 FLAG_CLR (Address = 13h) [Reset = 00h]

FLAG_CLR is shown in Figure 7-17 and described in Table 7-16.

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Figure 7-17 FLAG_CLR
76543210
RESERVEDTSD_CLRPOR_CLR
R-0hW1C-0hW1C-0h
Table 7-16 FLAG_CLR Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h Reserved
1TSD_CLRW1C0h Write 1 to clear TSD flag.
0POR_CLRW1C0h Write 1 to clear POR flag.

7.6.10 OUT0_DC (Address = 14h) [Reset = 00h]

OUT0_DC is shown in Figure 7-18 and described in Table 7-17.

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Figure 7-18 OUT0_DC
76543210
OUT0_DC
R/W-0h
Table 7-17 OUT0_DC Field Descriptions
BitFieldTypeResetDescription
7-0OUT0_DCR/W0h OUT0 DC setting.

7.6.11 OUT1_DC (Address = 15h) [Reset = 00h]

OUT1_DC is shown in Figure 7-19 and described in Table 7-18.

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Figure 7-19 OUT1_DC
76543210
OUT1_DC
R/W-0h
Table 7-18 OUT1_DC Field Descriptions
BitFieldTypeResetDescription
7-0OUT1_DCR/W0h OUT1 DC setting.

7.6.12 OUT2_DC (Address = 16h) [Reset = 00h]

OUT2_DC is shown in Figure 7-20 and described in Table 7-19.

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Figure 7-20 OUT2_DC
76543210
OUT2_DC
R/W-0h
Table 7-19 OUT2_DC Field Descriptions
BitFieldTypeResetDescription
7-0OUT2_DCR/W0h OUT2 DC setting.

7.6.13 OUT3_DC (Address = 17h) [Reset = 00h]

OUT3_DC is shown in Figure 7-21 and described in Table 7-20.

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Figure 7-21 OUT3_DC
76543210
OUT3_DC
R/W-0h
Table 7-20 OUT3_DC Field Descriptions
BitFieldTypeResetDescription
7-0OUT3_DCR/W0h OUT3 DC setting.

7.6.14 OUT0_MANUAL_PWM (Address = 18h) [Reset = 00h]

OUT0_MANUAL_PWM is shown in Figure 7-22 and described in Table 7-21.

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Figure 7-22 OUT0_MANUAL_PWM
76543210
OUT0_MANUAL_PWM
R/W-0h
Table 7-21 OUT0_MANUAL_PWM Field Descriptions
BitFieldTypeResetDescription
7-0OUT0_MANUAL_PWMR/W0h OUT0 manual PWM setting.
0x00 = 0%
...
0x80 = 50%
...
0xFF = 100%

7.6.15 OUT1_MANUAL_PWM (Address = 19h) [Reset = 00h]

OUT1_MANUAL_PWM is shown in Figure 7-23 and described in Table 7-22.

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Figure 7-23 OUT1_MANUAL_PWM
76543210
OUT1_MANUAL_PWM
R/W-0h
Table 7-22 OUT1_MANUAL_PWM Field Descriptions
BitFieldTypeResetDescription
7-0OUT1_MANUAL_PWMR/W0h OUT1 manual PWM setting.
0x00 = 0%
...
0x80 = 50%
...
0xFF = 100%

7.6.16 OUT2_MANUAL_PWM (Address = 1Ah) [Reset = 00h]

OUT2_MANUAL_PWM is shown in Figure 7-24 and described in Table 7-23.

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Figure 7-24 OUT2_MANUAL_PWM
76543210
OUT2_MANUAL_PWM
R/W-0h
Table 7-23 OUT2_MANUAL_PWM Field Descriptions
BitFieldTypeResetDescription
7-0OUT2_MANUAL_PWMR/W0h OUT2 manual PWM setting.
0x00 = 0%
...
0x80 = 50%
...
0xFF = 100%

7.6.17 OUT3_MANUAL_PWM (Address = 1Bh) [Reset = 00h]

OUT3_MANUAL_PWM is shown in Figure 7-25 and described in Table 7-24.

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Figure 7-25 OUT3_MANUAL_PWM
76543210
OUT3_MANUAL_PWM
R/W-0h
Table 7-24 OUT3_MANUAL_PWM Field Descriptions
BitFieldTypeResetDescription
7-0OUT3_MANUAL_PWMR/W0h OUT3 manual PWM setting.
0x00 = 0%
...
0x80 = 50%
...
0xFF = 100%

7.6.18 FLAG (Address = 40h) [Reset = 00h]

FLAG is shown in Figure 7-26 and described in Table 7-25.

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Figure 7-26 FLAG
76543210
RESERVEDTSDPOR
R-0hR-0hR-0h
Table 7-25 FLAG Field Descriptions
BitFieldTypeResetDescription
7-2RESERVEDR0h Reserved
1TSDR0h TSD flag.
0x0 = TSD is not triggered
0x1 = TSD is triggered
0PORR0h POR flag.
0x0 = POR is not triggered
0x1 = POR is triggered