SNVSCQ9 November   2025 LM68425-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Device Comparison Table
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Voltage Selection
      2. 7.3.2 EN Pin and Use as VIN UVLO
      3. 7.3.3 Mode Selection
        1. 7.3.3.1 MODE/SYNC/TEMP Pin Uses for Synchronization
        2. 7.3.3.2 Clock Locking
      4. 7.3.4 Adjustable Switching Frequency
      5. 7.3.5 Dual Random Spread Spectrum (DRSS)
      6. 7.3.6 Internal LDO, VCC UVLO, and BIAS Input
      7. 7.3.7 Bootstrap Voltage (BST Pin)
      8. 7.3.8 Soft Start and Recovery From Dropout
      9. 7.3.9 Safety Features
        1. 7.3.9.1 Power-Good Monitor
        2. 7.3.9.2 Redundant VOUT Monitor
        3. 7.3.9.3 Fault Output
        4. 7.3.9.4 Voltage Reference Monitor
        5. 7.3.9.5 Start-Up Diagnostics
        6. 7.3.9.6 Overcurrent and Short-Circuit Protection
        7. 7.3.9.7 Hiccup
        8. 7.3.9.8 Thermal Shutdown
        9. 7.3.9.9 Redundant Temperature Sensor
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Peak Current Mode Operation
        2. 7.4.2.2 Auto Mode Operation
          1. 7.4.2.2.1 Diode Emulation
        3. 7.4.2.3 FPWM Mode Operation
        4. 7.4.2.4 Dropout
        5. 7.4.2.5 Recovery from Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Custom Design With WEBENCH® Tools
        2. 8.2.2.2 Choosing the Switching Frequency
        3. 8.2.2.3 FB for Adjustable or Fixed Output Voltage Mode
        4. 8.2.2.4 Inductor Selection
        5. 8.2.2.5 Output Capacitor Selection
        6. 8.2.2.6 Input Capacitor Selection
        7. 8.2.2.7 CBOOT
        8. 8.2.2.8 External UVLO
        9. 8.2.2.9 Maximum Ambient Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Ground and Thermal Considerations
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.9.3 Fault Output

In addition to serving as an output for the redundant VOUT monitor, the LM684x5-Q1 nFAULT pin also reports faults detected by the startup diagnostics circuit and the internal reference monitor. The nFAULT pin is a 42V open drain output that can directly interface to upstream protection circuits as shown in Figure 7-10. The following faults are reported on the nFAULT pin:

  • Output overvoltage events detected by the redundant VOUT monitor.
  • Failures in the FB or VSNS paths (pin fail-open, pin fail-short, resistor fail-open, or parametric shifts) detected by the redundant VOUT monitor.
  • Internal voltage reference or redundant voltage reference faults detected by the voltage reference monitor.
  • Connection issues with the FB, VSNS pins detected by the startup diagnostics circuit.
  • Power-good functionality issues detected by the start-up diagnostics circuit.

As soon as any of the above faults are detected, the switching action is stopped immediately and the nFAULT pin latched low (<VOL(nFAULT)) . The EN pin toggle is required to clear the latch and restart the switching action.

The LM684x5-Q1 also includes provisions for implementing an auto-retry scheme as shown in the following figure to eliminate the need for user intervention in case of transient or temporary faults.


LM68415-Q1 LM68425-Q1 Redundant Monitoring of an Adjustable VOUT With an Auto-Retry Scheme
Figure 7-10 Redundant Monitoring of an Adjustable VOUT With an Auto-Retry Scheme

The scheme uses an internal counter and an external circuit consisting of M1, M2, C1, R1, and R2 to auto-retry the startup sequence after fault detection. The following describes the behavior of the auto-retry scheme:

  1. After a fault detection, an internal fault counter increments, the nFAULT pin latches low and drives the base of the M1 (PNP) low.
  2. The M1 turns on and pulls the base of the M2 (NPN) high.
  3. The M2 turns on and pulls the EN pin low disabling the device and clearing the nFAULT latch.
  4. The device restarts, going through the full startup diagnostics and soft-start sequences. If no faults are detected, the device operates in steady state.
  5. If the fault is still present, the device repeats steps 1 – 4 until the fault counter advances to the count of four.
  6. The nFAULT pin is latched low, now requiring the VIN pin toggle or battery disconnect to clear the latch.

TI recommends a 100kΩ pullup resistor from the nFAULT pin to the relevant logic rail not greater than 42V.