SNVU739A October   2020  – August 2021 LM5157-Q1

 

  1.   Trademarks
  2. 1Features and Electrical Performance
    1. 1.1 Electrical Parameters
    2. 1.2 Configuration Points
  3. 2Application Schematic
  4. 3EVM Picture
  5. 4Test Setup and Procedure
    1. 4.1 Test Setup
    2. 4.2 Test Equipment
  6. 5Test Results
    1. 5.1 Efficiency Curve
    2. 5.2 Load Regulation Curve
    3. 5.3 Thermal Performance
    4. 5.4 Steady State Waveforms
    5. 5.5 Start-Up Waveforms
    6. 5.6 Load Transient Waveforms
    7. 5.7 AC Loop Response Curves
  7. 6Design Files
    1. 6.1 Schematic
    2. 6.2 Bill of Materials
  8. 7Revision History

Design Files

Figure 6-1 through Figure 6-6 illustrate the EVM PCB layout images.

GUID-20210723-CA0I-26LP-LV2V-2DDLVMZFGFQ0-low.gifFigure 6-1 Top Layer and Silkscreen
GUID-20210723-CA0I-C3S5-6S7H-J4H3BLBSVBMM-low.gifFigure 6-3 Signal Layer 1
GUID-20210723-CA0I-MF6F-CPRN-3TKDPTFRD9XT-low.gifFigure 6-5 Bottom Layer
GUID-20210723-CA0I-PS7D-FJDG-DW97CN6DGPBR-low.gifFigure 6-2 Top Layer
GUID-20210723-CA0I-LSV7-1SXM-BHNT9JH4TDTS-low.gifFigure 6-4 Signal Layer 2
GUID-20210723-CA0I-HRJ5-5BP0-MN6W2XHLSGRW-low.gifFigure 6-6 Bottom Layer and Silkscreen (mirrored)