SNVU874A December   2024  – April 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Connector, Jumper, DIP switch and Test point Description
      1. 2.1.1 Connector Descriptions
      2. 2.1.2 Jumper Descriptions
      3. 2.1.3 DIP Switch Descriptions
      4. 2.1.4 Test Points Description
      5. 2.1.5 Easy to Use Features
  9. 3Implementation Results
    1. 3.1 Test Setup and Procedure
      1. 3.1.1 Test Setup
      2. 3.1.2 Test Procedure
      3. 3.1.3 Precautions
    2. 3.2 Performance Data and Results
      1. 3.2.1 Efficiency
      2. 3.2.2 Steady State Waveforms
      3. 3.2.3 Step Load Response
      4. 3.2.4 AC Loop Response Curve
      5. 3.2.5 Thermal Performance
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layers
    3. 4.3 Bill of Materials
  11. 5Additional Information
    1.     Trademarks
  12. 6Revision History

2.1.3 DIP Switch Descriptions

The CFG0 pin defines the dead time and the ATRK/DTRK pin 20μA current source for VOUT programming.

Table 2-3 CFG0 Pin Settings
Level Dead time (ns) 20μA ATRK current
1 14 on
2 30
3 50
4 75
5 100
6 125
7 150
8 200
9 18 off
10 30
11 50
12 75
13 100
14 125
15 150
16 200

The CFG1 pin setting defines the VOUT Over Voltage Protection level, Clock Dithering, the 120% input current limit protection (ICL_latch) operation, and the power good pin behavior.

Table 2-4 CFG1 Pin Settings
Level OVP Bit 0 Clock Dithering Mode ICL_latch PGOODOVP_enable
1 0 enabled (DRSS) disabled disabled
2 1
3 0 enabled
4 1
5 0 enabled disabled
6 1
7 0 enabled
8 1
9 0 disabled disabled disabled
10 1
11 0 enabled
12 1
13 0 enabled disabled
14 1
15 0 enabled
16 1

The CFG2 pin defines the VOUT Over Voltage Protection level, if the device uses the internal clock generator or an external clock applied at the SYNCIN pin. It configures as well if the device is a single device or part of a dual device configuration, the SYNCIN and SYNCOUT pin is enabled/disabled accordingly. During clock synchronization, the clock dither function is disabled.

Table 2-5 CFG2 Pin Settings
Level OVP Bit 1 SYNCIN Clock Dithering
1 0 off CFG1 pin
2 1
3 0
4 1 on disabled
≥5 0
Table 2-6 Overvoltage Protection Level Selection
OVP Level OVP Bit 1 OVP Bit 0
64V 0 0
50V 0 1
35V 1 0
28.5V 1 1

S1 through S6 are 8-bit DIP switches.

  • S1 and S2 are for CFG0
    • S1-postion 1 selects Level 1, …, S1-postion 8 selects Level 8
    • S2-postion 1 selects Level 9, …, S2-postion 8 selects Level 16
  • S3 and S4 are for CFG1
    • S3-postion 1 selects Level 1, …, S3-postion 8 selects Level 8
    • S4-postion 1 selects Level 9, …, S4-postion 8 selects Level 16
  • S5 and S6 are for CFG2
    • S5-postion 1 selects Level 1, …, S5-postion 8 selects Level 8
    • S6-postion 1 selects Level 9, …, S6-postion 8 selects Level 16

Select position 3 for S1 by default. This selects Level 3 for CFG0:

  • Dead time = 50ns
  • 20μA ATRK current source = on

Select position 2 for S4 by default. This selects Level 10 for CFG1:

  • OVP bit 0 = 1
  • DRSS = disabled
  • ICL_latch = disabled
  • PGOODOVP_enable = disabled

Select position 1 for S5 by default. This selects Level 1 for CFG2:

  • OVP bit 1 = 0
  • Single chip
  • Phase shift = 180°
  • SYNCIN = off
  • SYNCOUT = off

OVP bit 1 = 0 and OVP bit 0 = 1 select OVP level to 50V.

Note: The EVM can be damaged if lower than 50ns dead time is selected or operate with Vout>50V. Select OVP level no more than 50V.