SNVU930 November   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Connector, Jumper, DIP switch and Test point Description
      1. 2.1.1 Connector Descriptions
      2. 2.1.2 Jumper Descriptions
      3. 2.1.3 DIP Switch Descriptions
      4. 2.1.4 Test Points Description
  9. 3Easy to Use Features
  10. 4Implementation Results
    1. 4.1 Test Setup and Procedure
      1. 4.1.1 Test Setup
      2. 4.1.2 Test Setup for Stacking 2 EVMs
      3. 4.1.3 Test Procedure
      4. 4.1.4 Precautions
  11. 5Application Curves
    1. 5.1 Efficiency
    2. 5.2 Steady State Waveforms
    3. 5.3 Step Load Response
    4. 5.4 AC Loop Response Curve
    5. 5.5 Thermal Performance
  12. 6Hardware Design Files
    1. 6.1 Schematic
    2. 6.2 PCB Layers
    3. 6.3 Bill of Materials
  13. 7Additional Information
    1.     Trademarks

2.1.3 DIP Switch Descriptions

The CFG0 pin defines the deadtime and the ATRK/DTRK pin 20μA current source for VOUT programming.

Table 2-3 CFG0 Pin Settings
LevelDeadtime [ns]20μA ATRK Current
118on
230on
350on
475on
5100on
6125on
7150on
8200on
918off
1030off
1150off
1275off
13100off
14125off
15150off
16200off

The CFG1 pin setting defines the VOUT Over Voltage Protection level, Clock Dithering, the 120% input current limit protection (ICL_latch) operation and the power good pin behavior.

Table 2-4 CFG1 Pin Settings
LevelOVP Bit 0Clock Dithering ModeICL_latchPGOODOVP_enable
10enabled (DRSS)disableddisabled
21enabled (DRSS)disableddisabled
30enabled (DRSS)disabledenabled
41enabled (DRSS)disabledenabled
50enabled (DRSS)enableddisabled
61enabled (DRSS)enableddisabled
70enabled (DRSS)enabledenabled
81enabled (DRSS)enabledenabled
90disableddisableddisabled
101disableddisableddisabled
110disableddisabledenabled
121disableddisabledenabled
130disabledenableddisabled
141disabledenableddisabled
150disabledenabledenabled
161disabledenabledenabled

The CFG2 pin defines the VOUT Over Voltage Protection level, if the device uses the internal clock generator or an external clock applied at the SYNCIN pin. The CFG2 pin also configures if the device is a single device or part of a dual device configuration, the SYNCIN and SYNCOUT pin is enabled/disabled accordingly. During clock synchronization the clock dither function is disabled.

Table 2-5 CFG2 Pin Settings
LevelOVP bit 1Single / Dual Chip Phase 2 Phase ShiftSYNCINSYNCOUTSYNCOUT Phase ShiftClock Dithering
10single180°offoffoffCFG1 pin
21
30
41single ext. clock180°onoffoffdisabled
50
61
70primary 3-phase240°offon120°CFG1 pin
81
90primary 4-phase180°offon90°CFG1 pin
101
110primary ext. clock 3-phase240°onon120°disabled
121
130primary ext. clock 4-phase180°onon90°disabled
141
150secondary180°onoffoffdisabled
161

S1 through S6 are 8-bit DIP switches.

  • S1 and S2 are for CFG0
    • S1-postion 1 selects Level 1, …, S1-postion 8 selects Level 8
    • S2-postion 1 selects Level 9, …, S2-postion 8 selects Level 16
  • S3 and S4 are for CFG1
    • S3-postion 1 selects Level 1, …, S3-postion 8 selects Level 8
    • S4-postion 1 selects Level 9, …, S4-postion 8 selects Level 16
  • S5 and S6 are for CFG2
    • S5-postion 1 selects Level 1, …, S5-postion 8 selects Level 8
    • S6-postion 1 selects Level 9, …, S6-postion 8 selects Level 16
Select position 3 for S1 by default to set Level 3 for CFG0:
  • Deadtime = 50ns
  • 20μA ATRK current source = on

Note: The EVM is susceptible to damage if lower than 50ns deadtime is selected.

Select position 2 for S4 by default to set Level 10 for CFG1:

  • OVP bit 0 = 1
  • DRSS = disabled
  • ICL_latch = disabled
  • PGOODOVP_enable = disabled

Select position 1 for S5 by default to set Level 1 for CFG2:

  • OVP bit 1 = 0
  • Single chip
  • Phase shift = 180°
  • SYNCIN = off
  • SYNCOUT = off