SNVU948 July 2025 LM51770
| Reference Designator | Pins | Description | Default Connection |
|---|---|---|---|
| JP1 | Pin 1 to Pin 2 (GND) | Jumper in position GND and power save mode (PSM) is enabled. | |
| Pin 2 to Pin 3 (VCC) | Jumper in position VCC and FPWM mode is enabled. | * | |
| JP2 | Pin 1 to Pin 2 (GND) | Jumper in position GND (SYNC pin tied GND) and frequency synchronization is disabled. | * |
Open | Jumper removed and external clock feed in on the SYNC pin. SYNC is enabled. | ||
| Pin 2 to Pin 3 (VCC) | Jumper in position VCC (SYNC pin tied VCC) and frequency synchronization is disabled. | ||
| JP3 | Pin 1 to Pin 2 (GND) | Jumper in position GND (DTRK pin tied GND) and digital voltage tracking is disabled. | * |
| Open | Jumper removed and voltage feed in on the DTRK pin. DTRK is enabled in case the voltage on the DTRK pin is higher than the rising threshold of the VT(DTRK). | ||
| Pin 2 to Pin 3 (VCC) | Jumper in position VCC (DTRK pin tied VCC) and digital voltage tracking is disabled. | ||
| JP4 | Pin 1 to Pin 2 (VEXT) | Jumper in position VEXT and the input from J7-VEXT is connected to the BIAS pin. | |
| Pin 3 to Pin 4 (VIN) | Jumper in position VIN. VIN (J1) is connected to the BIAS pin. | * | |
| Pin 5 to Pin 6 (VOUT) | Jumper in position VOUT. VOUT (J2) is connected to the BIAS pin. | ||
| JP5 | Pin 1 to Pin 2 (GND) | Jumper in position GND (EN/UVLO pin tied GND). The LM51770 is disabled. | |
| Open | Jumper removed (the EN pin is tied to a resistor divider network consisting of R14 and R15). The EN/UVLO threshold is set with the resistor divider network. | * | |
| Pin 2 to Pin 3 (VIN) | Jumper in position VCC (EN/UVLO pin tied VCC). The LM51770 is enabled. | ||
| JP6 | Pin 1 / Pin2 | Connection point for loop stability measurement (Bode plot). | |
| Pin 3 | GND | ||
| Pin 4 to Pin 5 | Jumper in position selects internal feedback divider. |