SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

2.5.1.2 Digital/Analog I/O Power 3.3 V

Z11 simulations were performed on the 3.3 V digital and analog power net of the controlCard EVM to verify transient power margin. The simulation domain included the:

  • AM263x BGA (U1) 3.3V power and ground return BGA and fan-out
  • Internal power and ground return routing layers
  • Regulator output

Initial runs of these simulations showed that no BOM changes were needed to meet the maximum and minimum frequency bandwidth below Ztarget (see above sections). Only the initial simulation with the final chosen BOM iterations are shown below.

The simulations were divided between the VDDS33 digital 3.3 V plane and decoupling network and the VDDA33 analog 3.3 V traces and decoupling local to the design. The F dividing line between these simulations is the FL18 ferrite bead element was used to separate these two decoupling performance simulations.

GUID-20220808-SS0I-NWK8-MFZG-8RW6BCDDWKHW-low.png Figure 2-14 AM263x LaunchPad PDN Simulations – 3.3 V Digital/Analog I/O Power Simulation Domain (A)
GUID-20220808-SS0I-W7LV-LW30-LF3FKVH5XTT3-low.png Figure 2-15 AM263x LaunchPad PDN Simulations – 3.3 V Digital/Analog I/O Power Simulation Domain (layer 8, bottom)
GUID-20220808-SS0I-H7KT-VL1J-P3VLPGQQQJZD-low.png Figure 2-16 AM263x LaunchPad PDN Simulations – 3.3 V Digital I/O Power Simulated Z11
GUID-20220808-SS0I-ZVFG-BWBM-JKW7BXSNQQCC-low.png Figure 2-17 AM263x LaunchPad PDN Simulations – 3.3 V Analog I/O Power Simulated Z11