SPRABJ8B September   2022  – November 2023 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P4

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
    1. 1.1 Acronyms
  5. 2 Power
    1. 2.1 Discrete DC-DC Power Solution
    2. 2.2 Integrated PMIC Power Solution
    3. 2.3 Power Decoupling and Filtering
    4. 2.4 Power Consumption
    5. 2.5 Power Distribution Network
      1. 2.5.1 Simulations
        1. 2.5.1.1 Core Digital Power 1.2 V
        2. 2.5.1.2 Digital/Analog I/O Power 3.3 V
    6. 2.6 e-Fuse Power
  6. 3 Clocking
    1. 3.1 Crystal and Oscillator Input Options
    2. 3.2 Output Clock Generation
    3. 3.3 Crystal Selection and Shunt Capacitance
    4. 3.4 Crystal Placement and Routing
  7. 4 Resets
  8. 5 Bootstrapping
    1. 5.1 SOP Signal Implementation
    2. 5.2 OSPI/QSPI Memory Implementation
    3. 5.3 ROM OSPI/QSPI Boot Requirements
  9. 6 JTAG Emulators and Trace
  10. 7 Multiplexed Peripherals
  11. 8 Digital Peripherals
    1. 8.1 General Digital Peripheral Routing Guidelines
  12. 9 Analog Peripherals
    1. 9.1 General Analog Peripheral Routing Guidelines
      1. 9.1.1 Resolver ADC Routing Guidelines
  13. 10Layer Stackup
    1. 10.1 Key Stackup Features
  14. 11Vias
  15. 12BGA Power Fan-Out and Decoupling Placement
    1. 12.1 Ground Return
    2. 12.2 1.2 V Core Digital Power
      1. 12.2.1 Key Layout Considerations
    3. 12.3 3.3 V Digital and Analog Power
      1. 12.3.1 Key Layout Considerations
    4. 12.4 1.8 V Digital and Analog Power
      1. 12.4.1 Key Layout Considerations
  16. 13References
  17.   Revision History

12.3.1 Key Layout Considerations

  • Wide 15 mil traces should be used for all power and ground return via fan-out.
  • 3.3 V I/O power tends to be shared across multiple devices in the system, recommend routing with very wide power planes across the PCB to minimize IR drops to all components including the AM263x or AM263Px
  • A tightly coupled, adjacent ground return reference plane should be used for best transient performance and EMI coupling
  • A wide power plane entry that covers the BGA 3.3 V power pin areas should be used for minimal IR drop and best transient performance
  • Larger packaged, lower-frequency, bulk capacitance should be placed adjacent to MCU BGA with vias directly to power plane paths
  • Smaller packaged, higher-frequency decoupling capacitance should be placed directly on BGA fan-out vias with as small of a dog-bone to power and ground return vias as possible
GUID-20220808-SS0I-DSHK-KBV8-61MR3JQ361PM-low.png Figure 12-7 AM263x controlCARD Excerpt – 3.3 V Digital and Analog Power Planes on Layer 5 and Layer 6
GUID-20220808-SS0I-XKT6-3GSW-KZ6LMZGFC3C5-low.png Figure 12-8 AM263x controlCARD Excerpt – 3.3 V Digital I/O and Analog I/O BGA Pinout and Regulator Output
GUID-20220808-SS0I-KCQS-HGGV-ZZDWBTSZ7M9J-low.png Figure 12-9 AM263x controlCARD Excerpt – Common 3.3 V Plane Transition Vias
GUID-20220808-SS0I-HFRZ-NWXZ-SDZ0VSTPR7FK-low.png Figure 12-10 AM263x controlCARD Excerpt – 3.3 V Digital and Analog Planes Layer 6
GUID-20220808-SS0I-KCQS-HGGV-ZZDWBTSZ7M9J-low.png Figure 12-11 AM263x controlCARD Excerpt – 3.3 V Digital and Analog Power Decoupling Mounting, Layer 10