SPRABU8A May 2014 – July 2025 AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359
This section allows users to select the device revision, choose DDR type and loading, set a junction temperature (not ambient temperature) between 0°C and 105°C, power estimation mode, SmartReflex AVS (Adaptive Voltage Scaling) and Dual-Voltage I/O VDDSHVx voltages as shown in Table 2-1.
| Device Revision(1)(2) | PG2.1 |
| DDR Type | DDR3 |
| DDR Loading | 1 |
| Junction Temperature (°C) | 25 |
| Power Estimation Mode | Typ |
| Smart Reflex | off |
| VDDSHV1 Voltage (V) | 1.8 |
| VDDSHV2 Voltage (V) | 1.8 |
| VDDSHV3 Voltage (V) | 1.8 |
| VDDSHV4 Voltage (V) | 1.8 |
| VDDSHV5 Voltage (V) | 1.8 |
| VDDSH61 Voltage (V) | 1.8 |
| Power Mode | Active |
| Dynamic Power Switching | Off |
| Power Modes | Application State | Power Domains, Clocks, and Voltage Supply States |
|---|---|---|
| Active | All Features | Power supplies: All power supplies are ON. VDD_MPU = 1.1V (nom) VDD_CORE = 1.1V (nom) Clocks: Main Oscillator (OSC0) = ON All DPLLs are locked. Power domains: PD_PER = ON PD_MPU = ON PD = GFX = ON or OFF (depending on use case) PD_WKUP = ON DDR is active |
| Standby | DDR memory is in self-refresh and contents are preserved. Wakeup from any GPIO. Cortex™-A8 context and register contents are lost and must be saved before entering standby. On exit, context must be restored from DDR. For wakeup, boot ROM executes and branches to system resume. | Power supplies: All power supplies are ON. VDD_MPU = 0.95V (nom) VDD_CORE = 0.95V (nom) Clocks: Main Oscillator (OSC0) = ON All DPLLs are in bypass. Power domains: PD_PER = ON PD_MPU = OFF PD = GFX = OFF PD_WKUP = ON DDR is in self-refresh. |
| Deepsleep1 | On-chip peripheral registers are preserved. Cortex-A8 context/registers are lost, so the application needs to save them to the L3 OCMC RAM or DDR before entering DeepSleep. DDR is in self-refresh. For wakeup, boot ROM executes and branches to system resume. | Power supplies: All power supplies are ON. VDD_MPU = 0.95V (nom) VDD_CORE = 0.95V (nom) Clocks: Main Oscillator (OSC0) = OFF All DPLLs are in bypass. Power domains: PD_PER = ON PD_MPU = OFF PD = GFX = OFF PD_WKUP = ON DDR is in self-refresh. |
| Deepsleep0 | PD_PER peripheral and Cortex-A8/MPU register information are lost. On-chip peripheral register (context) information of PD-PER domain needs to be saved by application to SDRAM before entering this mode. DDR is in self-refresh. For wakeup, boot ROM executes and branches to peripheral context restore followed by system resume. | Power supplies: All power supplies are ON. VDD_MPU = 0.95V (nom) VDD_CORE = 0.95V (nom) Clocks: Main Oscillator (OSC0) = OFF All DPLLs are in bypass. Power domains: PD_PER = ON PD_MPU = OFF PD = GFX = OFF PD_WKUP = ON DDR is in self-refresh. |
| RTC-Only | RTC timer remains active and all other device functionality is disabled. | Power supplies: All power supplies are OFF except. VDDS_RTC, VDD_MPU = 0V VDD_CORE = 0V Clocks: Main Oscillator (OSC0) = OFF Power domains: All power domains are OFF. |
The spreadsheet presents information only for the full-featured devices in the AM335x family. However, since the spreadsheet breaks out the power consumption due to each module in the full-featured device, estimates for the other devices in the AM335x family can be obtained by setting zero for the modules not present in the device under consideration. This makes sure that active power from the non-applicable modules are not included in the power tally. The device differences are summarized in the overview section in AM335x Device Evaluation Wiki.