Sitara processor: Arm Cortex-A8, EtherCAT, PRU-ICSS, CAN
Product details
Parameters
Package | Pins | Size
Features
- Up to 1-GHz Sitara™ ARM® Cortex®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
- On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
- External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
- mDDR: 200-MHz Clock (400-MHz Data Rate)
- DDR2: 266-MHz Clock (532-MHz Data Rate)
- DDR3: 400-MHz Clock (800-MHz Data Rate)
- DDR3L: 400-MHz Clock (800-MHz Data Rate)
- 16-Bit Data Bus
- 1GB of Total Addressable Space
- Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
- Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
- Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
- Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
- Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
- Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
- Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
- 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
- 8KB of Instruction RAM With Single-Error Detection (Parity)
- 8KB of Data RAM With Single-Error Detection (Parity)
- Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
- Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
- One UART Port With Flow Control Pins, Supports up to 12 Mbps
- One Enhanced Capture (eCAP) Module
- Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
- One MDIO Port
- Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
- Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
- Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
- Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I2C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
- Power
- Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
- Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
- Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
- Dynamic Voltage Frequency Scaling (DVFS)
- Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
- Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
- Integrated Switch
- Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
- Ethernet MACs and Switch Can Operate Independent of Other Functions
- IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
- Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
- Transmit and Receive Clocks up to 50 MHz
- Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
- Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
- Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
- FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
- All UARTs Support IrDA and CIR Modes
- All UARTs Support RTS and CTS Flow Control
- UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
- Up to Two Chip Selects
- Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
- 1-, 4- and 8-Bit MMC, SD, SDIO Modes
- MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
- Up to 48-MHz Data Transfer Rate
- Supports Card Detect and Write Protect
- Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I2C Master and Slave Interfaces
- Standard Mode (up to 100 kHz)
- Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
- 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
- GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
- DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
- DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- SGX530 3D Graphics Engine
- Tile-Based Architecture Delivering up to 20 Million Polygons per Second
- Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
- Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
- Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
- Fine-Grained Task Switching, Load Balancing, and Power Management
- Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
- Programmable High-Quality Image Anti-Aliasing
- Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
- LCD Controller
- Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
- Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
- Integrated LCD Interface Display Driver (LIDD) Controller
- Integrated Raster Controller
- Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
- 512-Word Deep Internal FIFO
- Supported Display Types:
- Character Displays - Uses LIDD Controller to Program these Displays
- Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
- Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
- 12-Bit Successive Approximation Register (SAR) ADC
- 200K Samples per Second
- Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
- Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
- Up to Three 32-Bit eCAP Modules
- Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
- Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
- Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
- Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
- Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
- Production ID
- Device Part Number (Unique JTAG ID)
- Device Revision (Readable by Host ARM)
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
- Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
- DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
- Transfers to and from On-Chip Memories
- Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
- Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
- Mailbox Registers that Generate Interrupts
- Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
- Spinlock has 128 Software-Assigned Lock Registers
- Mailbox Registers that Generate Interrupts
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
- Security
- Crypto Hardware Accelerators (AES, SHA, RNG)
- Secure Boot (optional; requires custom part engagement with TI)
- Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
- Packages:
- 298-Pin S-PBGA-N298 Via Channel Package
(ZCE Suffix), 0.65-mm Ball Pitch - 324-Pin S-PBGA-N324 Package
(ZCZ Suffix), 0.80-mm Ball Pitch
- 298-Pin S-PBGA-N298 Via Channel Package
All trademarks are the property of their respective owners.
Description
The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux® and TI-RTOS are available free of charge from TI.
The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:
The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.
The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.
Technical documentation
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
The AM3359 Industrial Communications Engine (ICE) is a development platform targeted for systems that specifically focus on the industrial communications capabilities of the Sitara AM335x Arm® Cortex™-A8 processors.
The AM335x Arm Cortex-A8 processors integrate the Programmable Real-time Unit (PRU (...)
Features
Hardware Specifications
- AM3359 Arm® Cortex-A8 processors
- DDR3, NOR Flash, SPI Flash
- OLED display
- TPS65910 Power management
- USB cable for debug
- RoHS Compliant
Software and Tools
- Processor SDK
- Code Composer Studio Integrated Development Environment (IDE)
- Application stacks for industrial communication protocols
- (...)
Description
The AM335x starter kit (EVM-SK) provides a stable and affordable platform with Mainline Linux™ to quickly start evaluation of Sitara™ Arm® Cortex®-A8 AM335x processors (AM3351, AM3352, AM3354, AM3356, AM3358) and accelerate development for factory automation, building automation, smart grid, and various (...)
Features
- Hardware
- 256MB DDR3
- 4.3” Touch-screen LCD
- Connectivity
- Dual Gigabit Ethernet Ports with integrated switch
- Peripherals
- USB
- USB-UART
- USB-XDS100 emulator
Android navigation buttons - User configured LEDs
- Audio out
Description
Features
Hardware
- AM3358 Arm processor
- 1GB DDR3
- TPS65910 power management IC
- 7” touch screen LCD
Software
- Processor SDK
Connectivity
- 10/100 Ethernet (1)
- UART (4)
- SD/MMC (2)
- USB2.0 OTG/HOST (1/1)
- Audio in/out
- JTAG
- CAN (2)
Description
The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.
Features
- Designed to work with AM335x Processors
- Vin: 2.7V to 5.8V
- 3 DC/DC step-down (buck) converters
- 2 LDOs
- 2 load switches (also configurable as LDOs)
- White LED driver capable of driving up to 20 LEDs
- Linear battery charger
- Power path management for Lithium-ion/Lithium-Polymer battery, USB, and AC inputs
Description
The TPS65218EVM is a fully assembled platform for evaluating the performance of the TPS65218 power management device.
Features
- 2 battery backup supplies
- 3 Buck converters
- 1 Buck-Boost converter
- USB load switch
- General purpose LDO
- Low-voltage load switch
- High-voltage load switch
Description
Description
Learn more about bytes at work at http://www.bytesatwork.io/en.
Description
Description
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Description
Learn more (...)
Description
Description
Description
Octavo Systems is the leader in providing system-in-package (SiP) based solutions to innovators around the globe. The OSD335x family of SiP devices are the fastest and most cost-effective way to develop and deploy high performance embedded systems based on the Sitara™ AM335x Arm® (...)
Description
The phyBOARD®-AM335x features a phyCORE-AM335x System on Module (SOM), based on the TI Sitara™ AM335x, which is directly soldered onto a carrier board PCB. This “Direct Solder Connect” (DSC) of the SOM to carrier board reduces system costs by omitting board-to-board connectors (...)
Features
- phyCORE®-AM335x System on Module
- 2x 10/100 RMII Ethernet
- CAN, RS-232, USB, SD, WiFi, Audio, Display support
- 100 x 72 mm (pico-ITX Format)
Description
The phyCORE®-AM335x SOM supports the Texas Instruments Sitara™ AM335x family of processors which feature high processing performance, low power, and a highly integrated peripheral set enriched with cutting-edge graphics processing as well as real time protocol support. The 220-pin SOM (...)
Features
- PowerVR SGX530 3D graphics
- Industrial communications subsystem
- Up to 1 GB DDR3 / 2 GB NAND
- SD/SDIO/MMC, USB, CAN, UART, I2S, I2C, display, 10/100/1000 Mbit/s ethernet
- Industrial temperature -40°C to +85°C
Description
Description
Description
The TI PRU Cape is a BeagleBone Black add-on board that allows users get to know TI’s powerful Programmable Real-Time Unit (PRU) core and basic functionality. The PRU is a low-latency microcontroller subsystem integrated in the Sitara AM335x and AM437x family of devices. The PRU core is (...)
Features
- Temperature sensor monitoring using 1-wire interface
- LCD Connector for optional character display (not included). Compatible with Newhaven NHD-0208AZ-RN-YBW-33V
- Audio jack connection output
- Dual GPIO push button switch
- LEDs
PRUCAPE
- Expansion Connector- Connection to BeagleBone / BeagleBone Black
- UART (...)
Description
The WL1835MODCOM8 is one of the two evaluation boards for the TI WiLink 8 combo module family. For designs requiring performance in the 5 GHz band and extended temperature range, see the WL1837MODCOM8I.
The WL1835MODCOM8 Kit for Sitara EVMs easily enables customers to add (...)
Features
- WLAN, Bluetooth, BLE on a module board
- 100-pin board card
- Dimension 76.0 mm(L) x 31.0 mm(W)
- WLAN 2.4 GHz SISO (20- and 40-MHz channels), 2.4-GHz MIMO (20-MHz channels)
- Support for Bluetooth & BLE dual mode
- Seamless integration with TI Sitara and other application processors
- Design for TI AM335X (...)
Description
The WL1837MODCOM8I, which is compatible with many processors including TI’s (...)
Features
- WLAN, Bluetooth 4.1, BLE on a module board
- 100-pin board card
- Dimension 76.0 mm(L) x 31.0 mm(W)
- WLAN 2.4 & 5 GHz SISO (20- and 40- MHz channels), 2.4 GHz MIMO (20-MHz channels)
- Support for Bluetooth & BLE dual mode
- Seamless integration with TI Sitara and other application processors
- Design for TI AM335x (...)
Description
The Spectrum Digital XDS200 is the first model of the XDS200 family of debug probes (emulators) for TI processors. The XDS200 family features a balance of low cost with good performance between the super low cost XDS110 and the high performance XDS560v2, while supporting a wide variety of standards (...)
Features
The XDS200 is the mid-range family of JTAG debug probes (emulators) for TI processors. Designed to deliver good performance and the most common features that place it between the low cost XDS110 and the high performance XDS560v2, the XDS200 is the balanced solution to debug TI microcontrollers (...)
Description
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
Features
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
Description
The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).
The (...)
Features
-
XDS560v2 is the latest variant of the XDS560 family of high-performance debug probes (emulators) for TI processors. With the fastest speeds and most features of the entire XDS family, XDS560v2 is the most comprehensive solution to debug TI microcontrollers, processors and wireless connectivity (...)
Software development
Features
Linux features
- Open Linux support
- Linux kernel and Bootloaders
- File system
- Qt/Webkit application framework
- 3D graphics support
- Integrated WLAN and Bluetooth® support
- GUI-based application launcher
- Example applications, including:
- ARM benchmarks: Dhrystone, Linpack, Whetstone
- Webkit web browser
- Soft Wifi access (...)
TI’s dual-mode Bluetooth stack enables Bluetooth + Bluetooth Low Energy and is comprised of Single Mode and Dual Mode offerings implementing the Bluetooth 4.0/4.1/4.2 specification. The Bluetooth stack is fully Bluetooth Special Interest Group (SIG) qualified, certified and royalty-free (...)
Features
- Supports Dual-mode Bluetooth 4.0/4.10 - Bluetooth certified and royalty free
- 4.2 Low Energy Secure Connect supported
- Fully SIG qualified
- Protocols/Profiles can be selectively enabled/disabled
- Fully Documented API Interface
- Classic Profiles Available (varies between the different platforms, see specific (...)
Features
- PRU-ICSS firmware binary images and driver sources
- Third-party stacks and evaluation libraries
- Scripts to generate CCS projects
- Example application for evaluation
- Documentation (release notes, protocol data sheets, user guides, porting guides, etc.)
Refer to the protocol datasheets and release notes of (...)
Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)
Features
- Full, pre-certified solutions based on Sitara™ processors
- Years of industrial communciations expertise
- Toolkits for master and slave development available
CCS Uniflash is a standalone tool used to (...)
Design tools & simulation
- Visualize the device clock tree
- Interact with clock tree elements (...)
Features
Power Estimation Tool (PET) provides users the ability to gain insight in to the power consumption of select TI processors. The tool includes the ability for the user to choose multiple application scenarios and understand the power consumption as well as how advanced power saving techniques can be (...)
Reference designs
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
NFBGA (ZCZ) | 324 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
TI E2E™ forums with technical support from TI engineers
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