AM3357

NFBGA (ZCZ)

324

—

Up to 1-GHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- SGX530 3D Graphics Engine
  - Tile-Based Architecture Delivering up to 20 Million Polygons per Second
  - Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
  - Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
  - Programmable High-Quality Image Anti-Aliasing
  - Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
- LCD Controller
  - Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
  - Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
  - Integrated LCD Interface Display Driver (LIDD) Controller
  - Integrated Raster Controller
  - Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
  - 512-Word Deep Internal FIFO
  - Supported Display Types:
    - Character Displays - Uses LIDD Controller to Program these Displays
    - Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
    - Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
  - Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
- Up to Three 32-Bit eCAP Modules
  - Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
- Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Security
- Crypto Hardware Accelerators (AES, SHA, RNG)
- Secure Boot (optional; requires custom part engagement with TI)
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Packages:
- 298-Pin S-PBGA-N298 Via Channel Package
  (ZCE Suffix), 0.65-mm Ball Pitch
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

Up to 1-GHz Sitara™ ARM^® Cortex^®-A8 32‑Bit RISC Processor
- NEON™ SIMD Coprocessor
- 32KB of L1 Instruction and 32KB of Data Cache With Single-Error Detection (Parity)
- 256KB of L2 Cache With Error Correcting Code (ECC)
- 176KB of On-Chip Boot ROM
- 64KB of Dedicated RAM
- Emulation and Debug - JTAG
- Interrupt Controller (up to 128 Interrupt Requests)
On-Chip Memory (Shared L3 RAM)
- 64KB of General-Purpose On-Chip Memory Controller (OCMC) RAM
- Accessible to All Masters
- Supports Retention for Fast Wakeup
External Memory Interfaces (EMIF)
- mDDR(LPDDR), DDR2, DDR3, DDR3L Controller:
  - mDDR: 200-MHz Clock (400-MHz Data Rate)
  - DDR2: 266-MHz Clock (532-MHz Data Rate)
  - DDR3: 400-MHz Clock (800-MHz Data Rate)
  - DDR3L: 400-MHz Clock (800-MHz Data Rate)
  - 16-Bit Data Bus
  - 1GB of Total Addressable Space
  - Supports One x16 or Two x8 Memory Device Configurations
- General-Purpose Memory Controller (GPMC)
  - Flexible 8-Bit and 16-Bit Asynchronous Memory Interface With up to Seven Chip Selects (NAND, NOR, Muxed-NOR, SRAM)
  - Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
  - Uses Hamming Code to Support 1-Bit ECC
- Error Locator Module (ELM)
  - Used in Conjunction With the GPMC to Locate Addresses of Data Errors from Syndrome Polynomials Generated Using a BCH Algorithm
  - Supports 4-, 8-, and 16-Bit per 512-Byte Block Error Location Based on BCH Algorithms
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU-ICSS)
- Supports Protocols such as EtherCAT^®, PROFIBUS, PROFINET, EtherNet/IP™, and More
- Two Programmable Real-Time Units (PRUs)
  - 32-Bit Load/Store RISC Processor Capable of Running at 200 MHz
  - 8KB of Instruction RAM With Single-Error Detection (Parity)
  - 8KB of Data RAM With Single-Error Detection (Parity)
  - Single-Cycle 32-Bit Multiplier With 64-Bit Accumulator
  - Enhanced GPIO Module Provides Shift-In/Out Support and Parallel Latch on External Signal
- 12KB of Shared RAM With Single-Error Detection (Parity)
- Three 120-Byte Register Banks Accessible by Each PRU
- Interrupt Controller (INTC) for Handling System Input Events
- Local Interconnect Bus for Connecting Internal and External Masters to the Resources Inside the PRU-ICSS
- Peripherals Inside the PRU-ICSS:
  - One UART Port With Flow Control Pins, Supports up to 12 Mbps
  - One Enhanced Capture (eCAP) Module
  - Two MII Ethernet Ports that Support Industrial Ethernet, such as EtherCAT
  - One MDIO Port
Power, Reset, and Clock Management (PRCM) Module
- Controls the Entry and Exit of Stand-By and Deep-Sleep Modes
- Responsible for Sleep Sequencing, Power Domain Switch-Off Sequencing, Wake-Up Sequencing, and Power Domain Switch-On Sequencing
- Clocks
  - Integrated 15- to 35-MHz High-Frequency Oscillator Used to Generate a Reference Clock for Various System and Peripheral Clocks
  - Supports Individual Clock Enable and Disable Control for Subsystems and Peripherals to Facilitate Reduced Power Consumption
  - Five ADPLLs to Generate System Clocks (MPU Subsystem, DDR Interface, USB and Peripherals [MMC and SD, UART, SPI, I²C], L3, L4, Ethernet, GFX [SGX530], LCD Pixel Clock)
- Power
  - Two Nonswitchable Power Domains (Real-Time Clock [RTC], Wake-Up Logic [WAKEUP])
  - Three Switchable Power Domains (MPU Subsystem [MPU], SGX530 [GFX], Peripherals and Infrastructure [PER])
  - Implements SmartReflex™ Class 2B for Core Voltage Scaling Based On Die Temperature, Process Variation, and Performance (Adaptive Voltage Scaling [AVS])
  - Dynamic Voltage Frequency Scaling (DVFS)
Real-Time Clock (RTC)
- Real-Time Date (Day-Month-Year-Day of Week) and Time (Hours-Minutes-Seconds) Information
- Internal 32.768-kHz Oscillator, RTC Logic and 1.1-V Internal LDO
- Independent Power-on-Reset (RTC_PWRONRSTn) Input
- Dedicated Input Pin (EXT_WAKEUP) for External Wake Events
- Programmable Alarm Can be Used to Generate Internal Interrupts to the PRCM (for Wakeup) or Cortex-A8 (for Event Notification)
- Programmable Alarm Can be Used With External Output (PMIC_POWER_EN) to Enable the Power Management IC to Restore Non-RTC Power Domains
Peripherals
- Up to Two USB 2.0 High-Speed DRD (Dual-Role Device) Ports With Integrated PHY
- Up to Two Industrial Gigabit Ethernet MACs (10, 100, 1000 Mbps)
  - Integrated Switch
  - Each MAC Supports MII, RMII, RGMII, and MDIO Interfaces
  - Ethernet MACs and Switch Can Operate Independent of Other Functions
  - IEEE 1588v1 Precision Time Protocol (PTP)
- Up to Two Controller-Area Network (CAN) Ports
  - Supports CAN Version 2 Parts A and B
- Up to Two Multichannel Audio Serial Ports (McASPs)
  - Transmit and Receive Clocks up to 50 MHz
  - Up to Four Serial Data Pins per McASP Port With Independent TX and RX Clocks
  - Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
  - Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
  - FIFO Buffers for Transmit and Receive (256 Bytes)
- Up to Six UARTs
  - All UARTs Support IrDA and CIR Modes
  - All UARTs Support RTS and CTS Flow Control
  - UART1 Supports Full Modem Control
- Up to Two Master and Slave McSPI Serial Interfaces
  - Up to Two Chip Selects
  - Up to 48 MHz
- Up to Three MMC, SD, SDIO Ports
  - 1-, 4- and 8-Bit MMC, SD, SDIO Modes
  - MMCSD0 has Dedicated Power Rail for 1.8‑V or 3.3-V Operation
  - Up to 48-MHz Data Transfer Rate
  - Supports Card Detect and Write Protect
  - Complies With MMC4.3, SD, SDIO 2.0 Specifications
- Up to Three I²C Master and Slave Interfaces
  - Standard Mode (up to 100 kHz)
  - Fast Mode (up to 400 kHz)
- Up to Four Banks of General-Purpose I/O (GPIO) Pins
  - 32 GPIO Pins per Bank (Multiplexed With Other Functional Pins)
  - GPIO Pins Can be Used as Interrupt Inputs (up to Two Interrupt Inputs per Bank)
- Up to Three External DMA Event Inputs that can Also be Used as Interrupt Inputs
- Eight 32-Bit General-Purpose Timers
  - DMTIMER1 is a 1-ms Timer Used for Operating System (OS) Ticks
  - DMTIMER4–DMTIMER7 are Pinned Out
- One Watchdog Timer
- SGX530 3D Graphics Engine
  - Tile-Based Architecture Delivering up to 20 Million Polygons per Second
  - Universal Scalable Shader Engine (USSE) is a Multithreaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Advanced Shader Feature Set in Excess of Microsoft VS3.0, PS3.0, and OGL2.0
  - Industry Standard API Support of Direct3D Mobile, OGL-ES 1.1 and 2.0, and OpenMax
  - Fine-Grained Task Switching, Load Balancing, and Power Management
  - Advanced Geometry DMA-Driven Operation for Minimum CPU Interaction
  - Programmable High-Quality Image Anti-Aliasing
  - Fully Virtualized Memory Addressing for OS Operation in a Unified Memory Architecture
- LCD Controller
  - Up to 24-Bit Data Output; 8 Bits per Pixel (RGB)
  - Resolution up to 2048 × 2048 (With Maximum 126-MHz Pixel Clock)
  - Integrated LCD Interface Display Driver (LIDD) Controller
  - Integrated Raster Controller
  - Integrated DMA Engine to Pull Data from the External Frame Buffer Without Burdening the Processor via Interrupts or a Firmware Timer
  - 512-Word Deep Internal FIFO
  - Supported Display Types:
    - Character Displays - Uses LIDD Controller to Program these Displays
    - Passive Matrix LCD Displays - Uses LCD Raster Display Controller to Provide Timing and Data for Constant Graphics Refresh to a Passive Display
    - Active Matrix LCD Displays - Uses External Frame Buffer Space and the Internal DMA Engine to Drive Streaming Data to the Panel
- 12-Bit Successive Approximation Register (SAR) ADC
  - 200K Samples per Second
  - Input can be Selected from any of the Eight Analog Inputs Multiplexed Through an 8:1 Analog Switch
  - Can be Configured to Operate as a 4-Wire, 5-Wire, or 8-Wire Resistive Touch Screen Controller (TSC) Interface
- Up to Three 32-Bit eCAP Modules
  - Configurable as Three Capture Inputs or Three Auxiliary PWM Outputs
- Up to Three Enhanced High-Resolution PWM Modules (eHRPWMs)
  - Dedicated 16-Bit Time-Base Counter With Time and Frequency Controls
  - Configurable as Six Single-Ended, Six Dual-Edge Symmetric, or Three Dual-Edge Asymmetric Outputs
- Up to Three 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
Device Identification
- Contains Electrical Fuse Farm (FuseFarm) of Which Some Bits are Factory Programmable
  - Production ID
  - Device Part Number (Unique JTAG ID)
  - Device Revision (Readable by Host ARM)
Debug Interface Support
- JTAG and cJTAG for ARM (Cortex-A8 and PRCM), PRU-ICSS Debug
- Supports Device Boundary Scan
- Supports IEEE 1500
DMA
- On-Chip Enhanced DMA Controller (EDMA) has Three Third-Party Transfer Controllers (TPTCs) and One Third-Party Channel Controller (TPCC), Which Supports up to 64 Programmable Logical Channels and Eight QDMA Channels. EDMA is Used for:
  - Transfers to and from On-Chip Memories
  - Transfers to and from External Storage (EMIF, GPMC, Slave Peripherals)
Inter-Processor Communication (IPC)
- Integrates Hardware-Based Mailbox for IPC and Spinlock for Process Synchronization Between Cortex-A8, PRCM, and PRU-ICSS
  - Mailbox Registers that Generate Interrupts
    - Four Initiators (Cortex-A8, PRCM, PRU0, PRU1)
  - Spinlock has 128 Software-Assigned Lock Registers
Security
- Crypto Hardware Accelerators (AES, SHA, RNG)
- Secure Boot (optional; requires custom part engagement with TI)
Boot Modes
- Boot Mode is Selected Through Boot Configuration Pins Latched on the Rising Edge of the PWRONRSTn Reset Input Pin
Packages:
- 298-Pin S-PBGA-N298 Via Channel Package
  (ZCE Suffix), 0.65-mm Ball Pitch
- 324-Pin S-PBGA-N324 Package
  (ZCZ Suffix), 0.80-mm Ball Pitch

The AM335x microprocessors, based on the ARM Cortex-A8 processor, are enhanced with image, graphics processing, peripherals and industrial interface options such as EtherCAT and PROFIBUS. The devices support high-level operating systems (HLOS). Processor SDK Linux^® and TI-RTOS are available free of charge from TI.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The microprocessor unit (MPU) subsystem is based on the ARM Cortex-A8 processor and the PowerVR SGX™ Graphics Accelerator subsystem provides 3D graphics acceleration to support display and gaming effects.

The PRU-ICSS is separate from the ARM core, allowing independent operation and clocking for greater efficiency and flexibility. The PRU-ICSS enables additional peripheral interfaces and real-time protocols such as EtherCAT, PROFINET, EtherNet/IP, PROFIBUS, Ethernet Powerlink, Sercos, and others. Additionally, the programmable nature of the PRU-ICSS, along with its access to pins, events and all system-on-chip (SoC) resources, provides flexibility in implementing fast, real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of SoC.

The AM335x microprocessor contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

The contains the subsystems shown in the Functional Block Diagram and a brief description of each follows:

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	Type	Title	Date
*	Data sheet	AM335x Sitara™ Processors datasheet (Rev. L)	15 Nov 2019
*	Errata	AM335x Sitara Processors Silicon Errata (Revs 2.1, 2.0, 1.0) (Rev. I)	03 Jan 2017
*	User guide	AM335x and AMIC110 Sitara™ Processors Technical Reference Manual (Rev. Q)	13 Dec 2019
	White paper	Industry 4.0 서보 드라이브에 Sitara™ 프로세서 및 마이크로컨트롤러 활용 (Rev. C)	12 Jan 2022
	White paper	運用適合工業 4.0 Sitara™ 伺服驅動器的處理器與微控制器 (Rev. C)	12 Jan 2022
	Design guide	Discrete Power Solution for AM335x in 12mmx12mm Form-Factor Reference Design (Rev. A)	09 Nov 2021
	White paper	Utilizing Sitara Processors and Microcontrollers for Industry 4.0 Servo Drives (Rev. C)	06 Oct 2021
	Application note	Industrial Communication Protocols Supported on Sitara™ Processors (Rev. D)	30 Sep 2021
	Application note	PRU-ICSS Feature Comparison (Rev. E)	17 Aug 2021
	Application note	nfBGA Packaging (Rev. C)	17 May 2021
	Application note	Ethernet PHY Configuration Using MDIO for Industrial Applications (Rev. A)	07 May 2021
	White paper	Time sensitive networking for industrial automation (Rev. B)	20 Jan 2021
	More literature	From Start to Finish: A Product Development Roadmap for Sitara™ Processors	16 Dec 2020
	White paper	EtherCAT® on Sitara™ Processors (Rev. I)	28 Jul 2020
	White paper	EtherNet/IP on TI's Sitara AM335x Processors (Rev. D)	28 Jul 2020
	E-book	Ein Techniker-Leitfaden für Industrieroboter-Designs	25 Mar 2020
	User guide	Powering the AM335x, AM437x, and AM438x with TPS65218D0 (Rev. B)	27 Feb 2020
	E-book	E-book: An engineer’s guide to industrial robot designs	12 Feb 2020
	Application note	AM335x Schematic Checklist (Rev. A)	19 Dec 2019
	Application note	AM335x EMIF Tools	20 Sep 2019
	Application note	AM335x PMIC Selection Guide (Rev. A)	19 Sep 2019
	Application note	Programmable Logic Controllers — Security Threats and Solutions	13 Sep 2019
	More literature	Sitara™ processors + WiLink™ 8 Wi-Fi® + Bluetooth® combo connectivity (Rev. A)	30 Jul 2019
	White paper	Power optimization techniques for energy-efficient systems (Rev. A)	28 Jun 2019
	White paper	Sitara Processor Security (Rev. D)	09 May 2019
	Application note	Calculating Useful Lifetimes of Embedded Processors (Rev. B)	07 May 2019
	Application note	AM335x Hardware Design Guide	03 May 2019
	Application note	How to Port WOLFSSL Onto TI Sitara AM335 Starter Kit	24 Apr 2019
	User guide	Powering AMIC110, AMIC120, AM335x, and AM437x with TPS65216	11 Apr 2019
	User guide	AM335x ICE EVM Rev2.1 Hardware User Guide	21 Feb 2019
	Application note	Common EOS pitfalls in board design	13 Feb 2019
	Application note	PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A)	18 Jan 2019
	Application note	McASP Design Guide - Tips, Tricks, and Practical Examples	10 Jan 2019
	Application note	PRU Read Latencies (Rev. A)	21 Dec 2018
	Application note	PRU-ICSS Getting Starting Guide on Linux (Rev. A)	10 Dec 2018
	White paper	Ensuring real-time predictability (Rev. B)	04 Dec 2018
	Technical article	Bringing the next evolution of machine learning to the edge	27 Nov 2018
	Application note	PRU-ICSS EtherCAT Slave Troubleshooting Guide	07 Nov 2018
	Application note	PRU-ICSS / PRU_ICSSG Migration Guide	05 Nov 2018
	White paper	PROFINET on TI’s Sitara™ processors (Rev. D)	13 Oct 2018
	White paper	Secure Boot on embedded Sitara™ processors (Rev. A)	13 Oct 2018
	Application note	High-Speed Interface Layout Guidelines (Rev. H)	11 Oct 2018
	User guide	How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS	24 Sep 2018
	Technical article	How quality assurance on the Processor SDK can improve software scalability	22 Aug 2018
	White paper	An inside look at industrial Ethernet communication protocols (Rev. B)	01 Aug 2018
	Application note	HSR/PRP Solutions on Sitara Processors for Grid Substation Communication	17 Apr 2018
	Application note	Processor SDK RTOS Customization: Modifying Board library to change UART instanc (Rev. A)	28 Mar 2018
	User guide	Powering the AM335x With the TPS650250 (Rev. B)	14 Mar 2018
	White paper	Data concentrators: The core of energy and data management (Rev. A)	21 Feb 2018
	User guide	PRU Assembly Instruction User Guide	16 Feb 2018
	White paper	POWERLINK on TI Sitara Processors (Rev. A)	10 Jan 2018
	More literature	TI Sitara™ AM335x ARM® Cortex™-A8 Microprocessors (Rev. E)	19 Dec 2017
	User guide	TPS65910Ax User's Guide for AM335x Processors (Rev. F)	08 Dec 2017
	User guide	Sub-1 GHz Sensor-to-Cloud Linux® E14 Kit	16 Oct 2017
	Application note	Thermal Design Guide for DSP and Arm Application Processors (Rev. B)	14 Aug 2017
	Application note	Processor-SDK RTOS Power Management and Measurement	02 Aug 2017
	Application note	Sitara Linux ALSA DSP Microphone Array Voice Recognition	30 Jun 2017
	White paper	Connected sensors in industrial automation (Rev. B)	22 Jun 2017
	Application note	AM335x Power Estimation Tool	31 May 2017
	Application note	AM335x Reliability Considerations in PLC Applications (Rev. A)	27 Apr 2017
	Application note	AM335x Low Power Design Guide (Rev. A)	28 Feb 2017
	Technical article	New simple open real-time Ethernet (SORTE) protocol supports 4µs cycle time	21 Nov 2016
	White paper	Enable security and amp up chip performance w/ hardware-accelerated cryptograpy (Rev. A)	11 Aug 2016
	Technical article	How to select the right industrial Ethernet standard: Do you speak multiprotocol?	28 Jul 2016
	White paper	Building automation for enhanced energy and operational efficiency (Rev. A)	26 Oct 2015
	Application note	Plastic Ball Grid Array [PBGA] Application Note (Rev. B)	13 Aug 2015
	White paper	Profibus on AM335x and AM1810 Sitara ARM Microprocessor White Paper (Rev. B)	03 Mar 2015
	User guide	G3 Power Line Communication Data Concentrator on BeagleBone Black Design Guide	13 Nov 2014
	User guide	Powering the AM335x with the TPS65217x . (Rev. I)	06 Sep 2014
	White paper	Mainline Linux™ ensures stability and innovation	27 Mar 2014
	White paper	Scalable Solutions for HMI	21 Nov 2013
	White paper	Linaro Speeds Development in TI Linux SDKs	27 Aug 2013
	White paper	The Yocto Project:Changing the way embedded Linux software solutions are develop	14 Mar 2013
	White paper	Smart thermostats are a cool addition to the connected home	27 Sep 2012

Design & development

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Evaluation board

TMDSICE3359 — AM3359 Industrial Communications Engine

The AM3359 Industrial Communications Engine (ICE) is a development platform targeted for systems that specifically focus on the industrial communications capabilities of the Sitara AM335x Arm® Cortex™-A8 processors.

The AM335x Arm Cortex-A8 processors integrate the Programmable Real-time Unit (PRU) (...)

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TMDSSK3358 — AM335x starter kit

The AM335x starter kit (EVM-SK) provides a stable and affordable platform with Mainline Linux™ to quickly start evaluation of Sitara™ Arm® Cortex®-A8 AM335x processors (AM3351, AM3352, AM3354, AM3356, AM3358) and accelerate development for factory automation, building automation, smart grid, and (...)

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TMDXEVM3358 — AM335x evaluation module

The AM335x Evaluation Module (EVM) enables developers to immediately start evaluating the AM335x processor family (AM3351, AM3352, AM3354, AM3356, AM3358) and begin building applications for factory automation, building automation, grid infrastructure, and more.

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TPS65217CEVM — TPS65217C Evaluation Module

The TPS65217CEVM is a fully assembled platform for evaluating the performance of the TPS65217C power management device.

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TPS65218EVM-100 — TPS65218 Evaluation Module

The TPS65218EVM is a fully assembled platform for evaluating the performance of the TPS65218 power management device.