SPRABU8A May   2014  – July 2025 AM3352 , AM3354 , AM3356 , AM3357 , AM3358 , AM3359

 

  1.   1
  2.   AM335x Power Estimation Tool
  3.   Trademarks
  4. 1Introduction
  5. 2Input Spreadsheet
    1. 2.1 Macro Buttons
    2. 2.2 Section A: High-Level System Configuration
    3. 2.3 Section B: Processors
    4. 2.4 Section C: Peripherals
    5. 2.5 Section D: Analog Modules
  6. 3Spreadsheet Upload
  7. 4Power Analysis Report
    1. 4.1 Power Estimation Report Sheet
    2. 4.2 Module Utilization Sheet
  8. 5Summary
  9. 6References
  10. 7Revision History

2.3 Section B: Processors

This section allows users to set an operating performance point (OPP) for MPU domain and CORE domain, MPU utilization and SGX utilization as shown in Table 2-3.

Table 2-3 Section B of the AM335x Input Spreadsheet
CORE OPP OPP100
MPU OPP OPP100
MPU Frequency (Mhz) 600
ARM Subsystem Utilization %
Cortex-A8 0
Cortex-A8 NEON 0
SGX Subsystem (for SGX-enabled devices only) Utilization %
SGX 0

The OPP options supported for the MPU voltage domain (VDD_MPU) and the CORE voltage domain (VDD_CORE) are shown in the following tables.

Table 2-4 PG1.0 VDD_CORE Operating Performance Points for ZCZ Package
VDD_CORE OPP Device Rev Blank(1) VDD_CORE DDR3, DDR3L [2] DDR2 [2] mDDR [2] L3 and L4
MIN NOM MAX
OPP100 1.056V 1.100V 1.144V 400MHz 266MHz 200MHz 200MHz and 100MHz
OPP50 0.912V 0.950V 0.988V — 125MHz 90MHz 100MHZ and 50MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
Table 2-5 PG1.0 VDD_MPU Operating Performance Points for ZCZ Package
VDD_CORE OPP
Device Rev Blank(1)		 VDD_MPU ARM (A8)
MIN NOM MAX
Turbo 1.210V 1.260V 1.326V 720MHz
OPP120 1.152V 1.200V 1.248V 600MHz
OPP100 [2] 1.056V 1.100V 1.144V 500MHz
OPP100 [3] 1.056V 1.100V 1.144V 275MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Applies to all orderable AM335_ZCZ_50 (500MHz speed grade) or higher devices.
(3) Applies to all orderable AM335_ZCZ_27 (275MHz speed grade) devices.
Table 2-6 PG1.0 VDD_CORE Operating Performance Points for ZCE Package
VDD_CORE OPP Rev "A" or Newer(1) VDD_MPU [2] ARM (A8) DDR3,
DDR3L [3]		 DDR2 [3] mDDR [3] L3 and L4
MIN NOM MAX
OPP100 1.056V 1.100V 1.144V 500MHz 400MHz 266MHz 200MHz 200MHz and 100MHz
OPP100 1.056V 1.100V 1.144V 275MHz 400MHz 266MHz 200MHz 200MHz and 100MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is emerged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
Table 2-7 PG2.1 VDD_CORE Operating Performance Points for ZCZ Package
VDD_MPP OPP Rev A or Newer(1) VDD_CORE DDR3, DDR3L [2] DDR2 [2] mDDR [2] L3 and L4
MIN NOM MAX
OPP100 1.056V 1.100V 1.144V 400MHz 266MHz 200MHz 200MHz and 100MHz
OPP50 0.912V 0.950V 0.988V — 125MHz 90MHz 100MHZ and 50MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.
Table 2-8 PG2.1 VDD_MPU Operating Performance Points for ZCZ Package
VDD_CORE OPP
Rev A or Newer(1)		 VDD_MPU ARM (A8)
MIN NOM MAX
Nitro 1.272V 1.325V 1.378V 1GHz
Turbo 1.210V 1.260V 1.326V 800MHz
OPP120 1.152V 1.200V 1.248V 720MHz
OPP100 [2] 1.056V 1.100V 1.144V 600MHz
OPP100 [3] 1.056V 1.100V 1.144V 300MHz
OPP50 0.912V 0.950V 0.988V 300MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) Applies to all orderable AM335_ZCZ_50 (500MHz speed grade) or higher devices.
(3) Applies to all orderable AM335_ZCZ_27 (275MHz speed grade) devices.
Table 2-9 PG2.1 VDD_CORE Operating Performance Points for ZCE Package
VDD_CORE OPP Device Rev Blank(1) VDD_MPU [2] ARM (A8) DDR3,
DDR3L [3]		 DDR2 [3] mDDR [3] L3 and L4
MIN NOM MAX
OPP100 1.056V 1.100V 1.144V 600MHz 400MHz 266MHz 200MHz 200MHz and 100MHz
OPP100 1.056V 1.100V 1.144V 300MHz 400MHz 266MHz 200MHz 200MHz and 100MHz
OPP50 0.912V 0.950V 0.988V 300MHz — 125MHz 90MHz 100MHz and 50MHz
(1) Frequencies in this table indicate maximum performance for a given OPP condition.
(2) VDD_MPU is emerged with VDD_CORE on the ZCE package.
(3) This parameter represents the maximum memory clock frequency. Since data is transferred on both edges of the clock, double-data rate (DDR), the maximum data rate is two times the maximum memory clock frequency defined in this table.

Module utilization is the percentage of the available MHz at the selected OPP needed to meet the scenario processing requirement.

A separate utilization entry is provided for the Cortex-A8 ARM processor and the NEON SIMD engine.

  • Cortex-A8 (ARM Cortex-A8 processor core): 0 - 100 %
  • Cortex-A8 NEON (General purpose SIMD engine): 0 - 100 %

For the graphics accelerator subsystem, a separate utilization entry is provided:

  • SGX (2D, 3D graphics accelerator engine): 0-100 %