SPRACI7A October   2018  – March 2022 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1 , TMS320F280040-Q1 , TMS320F280040C-Q1 , TMS320F280041 , TMS320F280041-Q1 , TMS320F280041C , TMS320F280041C-Q1 , TMS320F280045 , TMS320F280048-Q1 , TMS320F280048C-Q1 , TMS320F280049 , TMS320F280049-Q1 , TMS320F280049C , TMS320F280049C-Q1 , TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Overview of Memory Test Requirements
    2. 1.2 Terms and Definitions
  3. 2System Challenges to Memory Validation
    1. 2.1 Memory Test Flow
    2. 2.2 SRAM test Algorithmic Coverage
    3. 2.3 ROM Test Algorithmic Coverage
  4. 3Summary
  5. 4References
  6.   A M-POST Working in F28004x
    1.     A.1 Enabling of Test
    2.     A.2 M-POST Duration
    3.     A.3 M-POST Result
    4.     A.4 Periodic Self-Test
  7.   Revision History

A.1 Enabling of Test

Memory power on self test can be enabled by configuring the “Z1-OTP-BOOT-GPREG2” register as given in Table 5-1. All the requirements as mentioned in the ROM Code and Peripheral Booting section of the TRM needs to be adhered to for configuring these USER OTP bits.

Table 5-1 Z1-OTP-BOOT-GPREG2 Register Description
BitNameDescriptionBoot ROM Action
31-24KeyWrite 0x5A to these 8-bits to tell the boot ROM code that the bits in this register are validIf set to 0x5A, boot ROM uses the values in this register. If set to any other value, boot ROM ignores the values in this register.
23-8ReservedReservedNo action
7-6ReservedConfigures the memory power on self-test
0x0 - Execute self-test
0x1 - No action (Reserved)
0x2 - No action (Reserved)
0x3 - No action (Reserved)
5-4Error Status PinSets the GPIO pin to be used as the ERRORSTSNo action
0x0 – GPIO24
0x1 – GPIO28
0x2 – GPIO29
0x3 – ERRORSTS disabled (Default)Boot ROM configures the appropriate mux for the selected GPIO pin
3-0ReservedReservedNo action