Have you planned for the routing in the PCIE interface?
For detailed recommendations on proper PCIE SERDES signal connection and
routing, see the High-Speed Interface Layout Guidelines Application
Report. Add appropriate constraints or routing requirements
to your schematic. This will vary from tool to tool.
Have you connected the correct SERDES pairs for PCIE
operation? The AM65x includes two SERDES sets of transmit and receive
pairs named SERDES0 and SERDES1. Each can support a number of SERDES interfaces,
but the correct SERDES pairs must be used for the correct interface. SERDES0 and
SERDES1 can each support two separate PCIE 1-lane connections, but if a PCIE
2-lane connection is needed, the pairs must be connected in the correct order.
SERDES0 signals should be connected to the PERp0/n0 and PETp1/n1 pairs, and the
SERDES1 signals should be connected to the PERp1/n1 and PETp1/n1 signals for a
two-lane PCIE connection.
Have you included DC-blocking capacitors in the correct
location? DC-blocking capacitors are required for PCIE transmit and
receive pairs, but the capacitors should be placed closer to the PCIE
transmitter. If a PCIE connector is used in the design, the receive pair will be
connected directly to the connector. The DC-blocking caps for the receive pair
are present on the device connected to the PCIE connector.