Pull-up Resistors

• Are all pullups connected to the AM65x/DRA80x device pulled up to the correct I/O voltage? Pulling a signal to the wrong I/O voltage can cause leakage between the I/O rails of the device. Each terminal has an associated supply voltage used to power its I/O cell. This can be found in the AM654x Sitara™ Processors Data Manual, in the Ball Characteristics table, and in the DRA80xM Infotainment Applications Processor Silicon Revision 1.0.

Peripheral clock outputs:

• Put 22-Ω series resistors (close to processor) on the output clocks of the following modules: MMC, GPMC, McASP (both clock and frame sync), SPI, QSPI, and VOUT.

General Debug:

• Have you added visibility for the internal clocks? Output clocks MCU_SYSCLKOUT0, MCU_OBSCLK0, and SYSCLKOUT0 are available on pins. If these pins/signals are not muxed in your design for other purposes, have test points on them to allow the monitoring of internal clocks in support of hardware and software debugging.
• Have you added the ability to probe the MCU_PORz_OUT and PORz_OUT signals? Accessible test points for MCU_PORz_OUT and PORz_OUT are useful for debug.