Sitara processor: dual Arm Cortex-A53 & dual Arm Cortex-R5F, Gigabit PRU-ICSS, 3D graphics


Product details


Arm MHz (Max.) 1100 Arm DMIPS 5060 Ethernet MAC 10/100/1000, 6-Port 10/100/1000 PRU EMAC Serial I/O CAN-FD, I2C, McASP, McSPI, SPI, UART, USB Camera MIPI CSI-2, Parallel DRAM DDR3L, DDR4, LPDDR4 Memory ECC Security enabler Cryptographic acceleration, Device identity, Secure boot, Debug security, External memory protection, Trusted execution environment, Networking security, Secure storage, Software IP protection, Initial secure programming, Secure FW and SW update Display type MIPI DPI, OLDI Operating temperature range (C) -40 to 105 PCI/PCIe 2 PCIe Gen 3 Arm CPU 2 Arm Cortex-A53 open-in-new Find other AM6x Arm Cortex-A53 processors


  • Processor cores:
  • Dual- or quad-core Arm® Cortex®-A53 microprocessor subsystem at up to 1.1 GHz
    • Up to two dual-core or two single-core Arm® Cortex®-A53 clusters with 512KB L2 cache including SECDED
    • Each A53 core has 32KB L1 ICache and 32K L1 DCache
  • Dual-core Arm® Cortex®-R5F at up to 400 MHz
    • Supports lockstep mode
    • 16KB ICache, 16KB DCache, and 64KB RAM per R5F core
  • Industrial subsystem:
  • Three gigabit Industrial Communication Subsystems (PRU_ICSSG)
    • Up to two 10/100/1000 Ethernet ports per PRU_ICSSG
    • Supports two SGMII ports (2)
    • Compatibility with 10/100Mb PRU-ICSS
    • 24× PWMs per PRU_ICSSG
      • Cycle-by-cycle control
      • Enhanced trip control
    • 18× Sigma-delta filters per PRU_ICSSG
      • Short circuit logic
      • Over-current logic
    • 6× Multi-protocol position encoder interfaces per PRU_ICSSG
  • Memory subsystem:
  • Up to 2MB of on-chip L3 RAM with SECDED
  • Multi-core Shared Memory Controller (MSMC)
    • Up to 2MB (2 banks × 1MB) SRAM with SECDED
      • Shared coherent Level 2 or Level 3 memory-mapped SRAM
      • Shared coherent Level 3 Cache
    • 256-bit processor port bus and 40-bit physical address bus
    • Coherent unified bi-directional interfaces to connect to processors or device masters
    • L2, L3 Cache pre-warming and post flushing
    • Bandwidth management with starvation bound
    • One infrastructure master interface
    • Single external memory master interface
    • Supports distributed virtual system
    • Supports internal DMA engine – Data Routing Unit (DRU)
    • ECC error protection
  • DDR Subsystem (DDRSS)
    • Supports DDR3L/DDR4 memory types up to DDR-1600
    • Supports LPDDR4 memory type up to DDR-1333
    • 32-bit data bus and 7-bit SECDED bus
    • 32GB of total addressable space
  • General-Purpose Memory Controller (GPMC)
  • SafeTI™ semiconductor component:
  • Designed for functional safety applications
  • Developed according to the requirements of IEC 61508
  • Achieves systematic integrity of SIL-3
  • For the MCU safety island, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2
  • For the rest of the SoC, sufficient diagnostics are included to achieve random fault integrity requirements of SIL-2
  • In addition, sufficient architectural metrics are in place to achieve execution of SIL-3 applications given a proper safety concept (for example reciprocal comparison by software)
  • Functional safety manual available
  • Safety-related certification
    • Component level functional safety certification by TÜV SÜD [certification in progress]
  • Functional safety features:
    • ECC or parity on calculation-critical memories and internal bus interconnect
    • Firewalls to help provide Freedom From Interference (FFI)
      • Built-In Self-Test (BIST) for CPU, high-end timers, and on-chip RAM
    • Hardware error injection support for test-for-diagnostics
    • Error Signaling Modules (ESM) for capture of functional safety related errors
    • Voltage, temperature, and clock monitoring
    • Windowed and non-windowed watchdog timers in multiple clock domains
  • MCU island
    • Isolation of the dual-core Arm® Cortex®-R5F microprocessor subsystem
    • Separate voltage, clocks, resets, and dedicated peripherals
    • Internal MCSPI connection to the rest of SoC
  • Security:
  • Secure boot supported
    • Hardware-enforced root-of-trust
    • Support to switch root-of-trust via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 bits key sizes
      • 3DES – 56/112/168 bits key sizes
      • MD5, SHA1
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (public key accelerator) to assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm® TrustZone® based TEE
    • Extensive firewall support for isolation
    • Secure DMA path and interconnect
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-fly encryption and authentication support for OSPI interface
  • Networking security support for data (payload) encryption/authentication via packet based hardware cryptographic engine
  • Security coprocessor (DMSC) for key and security management, with dedicated device level interconnect for security
  • SoC services:
  • Device Management Security Controller (DMSC)
    • Centralized SoC system controller
    • Manages system services including initial boot, security, functional safety and clock/reset/power management
    • Power management controller for active and low power modes
    • Communication with various processing units over message manager
    • Simplified interface for optimizing unused peripherals
    • Tracing and debugging capability
  • Sixteen 32-bit general-purpose timers
  • Two data movement and control Navigator Subsystems (NAVSS)
    • Ring Accelerator (RA)
    • Unified DMA (UDMA)
    • Up to 2 Timer Managers (TM) (1024 timers each)
  • Multimedia:
  • Display subsystem
    • Two fully input-mapped overlay managers associated with two display outputs
    • One port MIPI® DPI parallel interface
    • One port OLDI
  • PowerVR® SGX544-MP1 3D Graphics Processing Unit (GPU)
  • One Camera Serial Interface-2 (MIPI CSI-2)
  • One port video capture: BT.656/1120 (no embedded sync)
  • High-speed interfaces:
  • One Gigabit Ethernet (CPSW) interface supporting
    • RMII (10/100) or RGMII (10/100/1000)
    • IEEE1588 (2008 Annex D, Annex E, Annex F) with 802.1AS PTP
    • Audio/video bridging (P802.1Qav/D6.0)
    • Energy-efficient Ethernet (802.3az)
    • Jumbo frames (2024 bytes)
    • Clause 45 MDIO PHY management
  • Two PCI-Express® (PCIe®) revision 3.1 subsystems (2)
    • Supports Gen2 (5.0GT/s) operation
    • Two independent 1-lane, or a single 2-lane port
    • Support for concurrent root-complex and/or end-point operation
  • USB 3.1 Dual-Role Device (DRD) subsystem (2)
    • One enhanced SuperSpeed Gen1 port
    • One USB 2.0 port
    • Each port independently configurable as USB host, USB peripheral, or USB DRD
  • General connectivity:
  • 6× Inter-Integrated Circuit (I2C™) ports
  • 5× configurable UART/IrDA/CIR modules
  • Two simultaneous flash interfaces configured as
    • Two OSPI flash interfaces
    • or HyperBus™ and OSPI1 flash interface
  • 2× 12-bit Analog-to-Digital Converters (ADC)
    • Up to 4 Msamples/s
    • Eight multiplexed analog inputs
  • 8× Multichannel Serial Peripheral Interfaces (MCSPI) controllers
    • Two with internal connections
    • Six with external interfaces
  • General-Purpose I/O (GPIO) pins
  • Control interfaces:
  • 6× Enhanced High Resolution Pulse-Width Modulator (EHRPWM) modules
  • One Enhanced Capture (ECAP) module
  • 3× Enhanced Quadrature Encoder Pulse (EQEP) modules
  • Automotive interfaces:
  • 2× Modular Controller Area Network (MCAN) modules with full CAN-FD support
  • Audio interfaces:
  • 3× Multichannel Audio Serial Port (MCASP) modules
  • Media and data storage:
  • 2× Multimedia Card™/Secure Digital® (MMC™/SD®) interfaces
  • Simplified power management:
  • Simplified power sequence with full support for dual voltage I/O
  • Integrated LDOs reduces power solution complexity
  • Integrated SDIO LDO for handling automatic voltage transition for SD interface
  • Integrated Power On Reset (POR) generation reducing power solution complexity
  • Integrated voltage supervisor for functional safety monitoring
  • Integrated power supply glitch detector for detecting fast power supply transients
  • Analog/system integration:
  • Integrated USB VBUS detection
  • Fail safe I/O for DDR RESET
  • All I/O pins drivers disabled during reset to avoid bus conflicts
  • Default I/O pulls disabled during reset to avoid system conflicts
  • Support dynamic I/O pinmux configuration change
  • System-on-Chip (SoC) architecture:
  • Supports primary boot from UART, I2C, OSPI, HyperBus, parallel NOR Flash, SD or eMMC™, USB, PCIe, and Ethernet interfaces
  • 28-nm CMOS technology
  • 23 mm × 23 mm, 0.8-mm pitch, 784-pin FCBGA (ACD)

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open-in-new Find other AM6x Arm Cortex-A53 processors


AM654x and AM652x Sitara™ processors are Arm® applications processors built to meet the complex processing needs of modern industry 4.0 embedded products.

The AM654x and AM652x devices combine four or two Arm® Cortex®-A53 cores with a dual Arm® Cortex®-R5F MCU subsystem which includes features intended to help customers achieve their functional safety goals for their end products and three Gigabit industrial communications subsystems (PRU_ICSSG) to create a SoC capable of high-performance industrial controls with industrial connectivity and processing for functional safety applications. AM65xx is currently undergoing assessment to be certified by TÜV SÜD according to IEC 61508.

The four Arm® Cortex®-A53 cores in the AM654x are arranged in two dual-core clusters with shared L2 memory to create two processing channels. The two Arm® Cortex®-A53 cores in the AM652x are available in a single dual-core cluster and two single-core cluster options. Extensive ECC is included on on-chip memory, peripherals, and interconnect for reliability. The SoC as a whole includes features intended to help customers design systems that can achieve their functional safety goals (assessment pending with TÜV SÜD). Cryptographic acceleration and secure boot are available on some AM654x and AM652x devices in addition to granular firewalls managed by the DMSC.

Programmability is provided by the Arm® Cortex®-A53 RISC CPUs with Arm® Neon™ extension, and the dual Arm® Cortex®-R5F MCU subsystem is available for general purpose use as two cores or it can be used in lockstep to help meet the needs of functional safety applications. The PRU_ICSSG subsystems can be used to provide up to six ports of industrial Ethernet such as Profinet IRT, TSN, Ethernet/IP or EtherCAT® (among many others), or they can be used for standard Gigabit Ethernet connectivity.

TI provides a complete set of software and development tools for the Arm® cores including Processor SDK Linux, Linux-RT, RTOS, and Android as well as C compilers and a debugging interface for visibility into source code execution. Applicable functional safety and security documentation will be made available to assist customers in developing their functional safety or security related systems.

open-in-new Find other AM6x Arm Cortex-A53 processors

More information

Prototype samples are available (X6580AACD). Request now

Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 36
Type Title Date
* Datasheet AM654x, AM652x Sitara™ Processors Silicon Revision 2.0 datasheet (Rev. A) Jan. 27, 2020
* Errata AM65x/DRA80xM Processors Silicon Revision 2.0/1.0 (Rev. E) Jun. 25, 2020
Technical articles How to affordably add EtherNet/IP, EtherCAT and PROFINET to an autonomous factory Aug. 24, 2020
Application notes MMC SW Tuning Algorithm Aug. 18, 2020
White papers EtherNet/IP on TI's Sitara AM335x Processors (Rev. D) Jul. 28, 2020
White papers Ein Techniker-Leitfaden für Industrieroboter-Designs Mar. 25, 2020
Application notes PRU-ICSS Feature Comparison (Rev. D) Mar. 09, 2020
Application notes AM65x/DRA80xM EMIF Tools (Rev. B) Mar. 04, 2020
White papers E-book: An engineer’s guide to industrial robot designs Feb. 12, 2020
Application notes AM65x/DRA80xM Silicon Revision 1.0 to 2.0 Migration Guide Jan. 06, 2020
User guides AM65x/DRA80xM Processors Technical Reference Manual (Rev. E) Dec. 18, 2019
Application notes AM65xx Time Synchronization Architecture Oct. 14, 2019
Technical articles Designing smarter remote terminal units for microgrids Oct. 02, 2019
Application notes Enabling Android Automotive on Your TI Development Board Jul. 12, 2019
Technical articles Security versus functional safety: a view from the Processor Software Development Kit May 31, 2019
Application notes AM65x DDR ECC Initialization and Testing Mar. 08, 2019
Application notes AM65x/DRA80xM DDR Board Design and Layout Guidelines (Rev. A) Mar. 07, 2019
White papers Virtualization for embedded industrial systems (Rev. B) Mar. 07, 2019
Application notes Integrating a WiLink8 Module with the AM65x EVM Jan. 29, 2019
Application notes PRU-ICSS Getting Started Guide on TI-RTOS (Rev. A) Jan. 18, 2019
Application notes PRU Read Latencies (Rev. A) Dec. 21, 2018
Application notes PRU-ICSS Getting Starting Guide on Linux (Rev. A) Dec. 10, 2018
White papers Ensuring real-time predictability (Rev. B) Dec. 04, 2018
Application notes AM65xx System Performance Nov. 30, 2018
White papers The state of functional safety in Industry 4.0 Nov. 27, 2018
Application notes PRU-ICSS / PRU_ICSSG Migration Guide Nov. 05, 2018
White papers Secure Boot on embedded Sitara™ processors (Rev. A) Oct. 13, 2018
Application notes Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. C) Oct. 12, 2018
White papers Designing industrial controls for Industry 4.0 with Sitara™ AM6x processors Oct. 11, 2018
Application notes Hardware Design Guide for AM65x/DRA80xM Devices Oct. 11, 2018
Application notes High-Speed Interface Layout Guidelines (Rev. H) Oct. 11, 2018
Application notes AM65x/DRA80x Schematic Checklist Oct. 04, 2018
Technical articles Simplified software development through the Processor SDK and tools Oct. 02, 2018
White papers Time sensitive networking for industrial automation (Rev. A) Oct. 02, 2018
User guides AM654x/DRA80xM BGA Escape Routing Stackup Aug. 29, 2018
White papers Designing Embedded Systems for High Reliability With Sitara AM6x Processors Aug. 28, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development


The 1280x800 LCD Display Accessory Kit is an add-on accessory for the AM65x IDK (TMDX654IDKEVM) to add touch and display functions for the evaluation of HMI, industrial PC, and other use cases requiring display. The 1280x800 LCD Display Accessory Kit comes bundled with the AM65x EVM (TMDX654GPEVM (...)


10.1" LCD screen (1280 x 800)
document-generic User guide

The AM65x Evaluation Module provides a platform to quickly start evaluation of Sitara™ Arm® Cortex®-A53 AM65x Processors (AM6548AM6546AM6528AM6527AM6526) and accelerate development for HMI, networking, patient monitoring, and other industrial applications. It is a development platform based on (...)

  • 3 gigabit Ethernet ports
  • 4GB DDR4 with ECC
  • On-board 16GB eMMC
  • On-board 512Mb OSPI Flash
  • 1-lane PCIe Gen3.1, USB 3.1, USB 2.0 and CSI-2 interfaces
document-generic User guide

Step 1: Order the IDK
Step 2: Download the Processor SDK
Step 3: Get the industrial protocol package
Step 4: Read the hardware user's guide

The AM65x Industrial Development Kit (IDK) is a development platform for evaluating the industrial communication and control capabilities of Sitara AM65x (...)

  • Up to 6 industrial gigabit Ethernet ports and 1 standard gigabit Ethernet port that can be used concurrently
  • 4GB DDR4 with ECC
  • Profibus connection and industrial I/O header
  • On-board 16GB eMMC
  • On-board 512Mb OSPI Flash
  • 2-lane PCIe Gen3.1, USB 2.0 and CSI-2 interfaces
Mistral Solutions AM65x System on Module (SOM)
Provided by Mistral Solutions Pvt. Ltd

The AM65x SOM from Mistral is an easy to use, compact, light-weight system on module (SOM) providing very high processing power for industrial applications. This module is based on Texas Instruments Sitara™ AM6548 SoC and is ideal for complex processing, connectivity and control required for (...)


The phyCORE®-AM65x module brings secure boot, multiprotocol gigabit industrial communication, graphics, functional safety features and time-sensitive networking (TSN) to the phyCORE® family. The phyCORE®-AM65x SOM is ideal for industrial communication systems, factory automation, edge (...)

  • DDR4 + optional ECC
  • Up to 32GB eMMC
  • Optional 2.4 or 5GHz certified WiFi solution
  • 1x 10/100/1000 Mbit/s + 6 PRU-ICSSG
  • Linux, Android, and TI-RTOS BSP
TQ Group Sitara SOMs
Provided by TQ-Group
TQ offers the complete range of services from development, through production and service right up to product life cycle management. The services cover assemblies, equipment and systems including hardware, software and mechanics. Customers can obtain all services from TQ on a modular basis as (...)

Software development

Processor SDK for AM65x Sitara processors – Linux, TI-RTOS, & Android support
PROCESSOR-SDK-AM65X Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos. All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly reuse and (...)

Linux features

  • Open Linux support
  • Linux kernel and Bootloaders
  • File system
  • Qt/Webkit application framework
  • 3D graphics support
  • GUI-based application launcher
  • Example applications
  • ARM benchmarks: Dhrystone, Linpack, Whetstone
  • Webkit web browser
  • Programmable Realtime Unit (PRU)
  • Host tools including Flash Tool (...)
Sitara External Memory Interface (EMIF) tool
SITARA-DDR-CONFIG-TOOL The Sitara™ EMIF tool is a software tool which provides an interface to configure the TI processors for accessing the external DDR memory devices. The tool also optimizes the Delay Locked Loop (DLL) settings to compensate for board routing skews. The results are output as EMIF configuration (...)
  • Supports all DDR memory types (LPDDR2, DDR3 and DDR3L DDR) available on devices
  • Supports HW leveling for DDR3/3L
  • Error checks for DRAM timings per JEDEC standard
  • Outputs EMIF configuration registers which can be directly used in Processor SDK and Code Composer Studio
Wind River Processors VxWorks and Linux operating systems
Provided by Wind River Systems Wind River is a global leader in delivering software for the Internet of Things (IoT). The company’s technology has been powering the safest, most secure devices in the world since 1981 and today is found in more than 2 billion products. Wind River offers a comprehensive edge-to-cloud product (...)
Code Composer Studio (CCS) Integrated Development Environment (IDE) for Sitara ARM Processors

Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor (...)

Safety Compiler Qualification Kit
SAFETI_CQKIT The Safety Compiler Qualification Kit was developed to assist customers in qualifying their use of the TI ARM, C6000, C7000 or C2000/CLA C/C++ Compiler to functional safety standards such as IEC 61508 and ISO 26262.

The Safety Compiler Qualification Kit:

  • does not require the user to run qualification (...)

The Safety Compiler Qualification Kit has been assessed by TÜV Nord to comply with both IEC 61508 and ISO 26262 and was developed in collaboration with by Validas, a consulting company that specializes in software tool qualification.

What's Included

Safety Compiler Qualification Kit includes: 

  • Safety (...)

Design tools & simulation

SPRM718.ZIP (2 KB) - Thermal Model
SPRM724.ZIP (12 KB) - BSDL Model
SPRM737.ZIP (19753 KB) - IBIS Model
Clock Tree Tool for Sitara, Automotive, Vision Analytics, & Digital Signal Processors
CLOCKTREETOOL The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree elements (...)
document-generic User guide
Pin mux tool
PINMUXTOOL The PinMux Utility is a software tool which provides a Graphical User Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI MPUs. Results are output as C header/code files that can be imported into software development kits (SDKs) or (...)

CAD/CAE symbols

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