SPRACQ1 May   2020 TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   Migration Between TMS320F2837x and TMS320F2838x
    1.     Trademarks
    2. 1 Feature Differences Between F2837x and F2838x
      1. 1.1 F2837x and F2838x Feature Comparison
    3. 2 PCB Hardware Changes
      1. 2.1 VDD Pin
      2. 2.2 VREGENZ Pin
      3. 2.3 Analog Pin Assignment
      4. 2.4 GPIO Pin Assignment
      5. 2.5 controlCARD
    4. 3 Feature Differences for System Consideration
      1. 3.1 New Features in F2838x Device
        1. 3.1.1  Fast Integer Division (FINTDIV)
        2. 3.1.2  VCRC Unit
        3. 3.1.3  EtherCAT Slave Controller (ESC)
        4. 3.1.4  Background CRC (BGCRC)
        5. 3.1.5  Diagnostic Features (PBIST/HWBIST)
        6. 3.1.6  Power Management Bus Module (PMBus)
        7. 3.1.7  Fast Serial Interface (FSI)
        8. 3.1.8  Embedded Real-time Analysis and Diagnostic (ERAD)
        9. 3.1.9  Dual-Clock Comparator (DCC)
        10. 3.1.10 Connectivity Manager (CM)
      2. 3.2 Features Differences/Enhancements in F2838x
        1. 3.2.1 System
          1. 3.2.1.1 Reset
          2. 3.2.1.2 Clocking
            1. 3.2.1.2.1 PLL
            2. 3.2.1.2.2 X1CNT
            3. 3.2.1.2.3 XCLKOUT
          3. 3.2.1.3 Pie Channel Mapping and Interrupt
            1. 3.2.1.3.1 SYS_ERR Interrupt
          4. 3.2.1.4 ERRORSTS Pin
        2. 3.2.2 Watchdog and NMI Watchdog
        3. 3.2.3 Memory
          1. 3.2.3.1 Internal SRAM/ROM
          2. 3.2.3.2 Flash
        4. 3.2.4 Dual Code Security Module (DCSM)
        5. 3.2.5 ROM Code and Peripheral Booting
        6. 3.2.6 External Memory Interface (EMIF)
        7. 3.2.7 Communication Modules
        8. 3.2.8 Control Modules
          1. 3.2.8.1 Enhanced Pulse Width Modulator (ePWM) and ePWM Sync Scheme
          2. 3.2.8.2 Enhanced Capture (eCAP)
          3. 3.2.8.3 Enhanced Quadrature Encoder Pulse (eQEP)
          4. 3.2.8.4 Sigma Delta Filter Module (SDFM)
        9. 3.2.9 Analog Modules
      3. 3.3 Other Device Changes
        1. 3.3.1 Bus Architecture
          1. 3.3.1.1 CLA and DMA Access
        2. 3.3.2 Control Law Accelerator (CLA)
        3. 3.3.3 Direct Memory Access (DMA)
      4. 3.4 Power Management
        1. 3.4.1 LDO/VREG
        2. 3.4.2 POR/BOR
      5. 3.5 Power Consumption
      6. 3.6 GPIO
        1. 3.6.1 GPIO Multiplexing Diagram
    5. 4 Application Code Migration From F2837x to F2838x
      1. 4.1 C2000Ware Driverlib Files
      2. 4.2 C2000Ware Header Files
      3. 4.3 Linker command Files
      4. 4.4 Minimum Compiler Version Requirement
      5. 4.5 EABI Support
        1. 4.5.1 Flash API
        2. 4.5.2 NoINIT Struct Fix (linker command)
        3. 4.5.3 Pre-Compiled Libraries
    6. 5 References

3.2.8.2 Enhanced Capture (eCAP)

The eCAP module on F2838x is "Type 2", which has some additional features compared to those on the F2837x devices ("Type 0"). F2838x also have HRCAP features available on some of eCAP input. Sync scheme for eCAP also has been changed on F2838x (same as ePWM Sync)

Table 13 provide the list of changes associated with eCAP module between F2837x and F2838x.

Table 13. eCAP Feature Comparison

Feature F2838x F2837x
Type Type 2 Type 0
Number of eCAP Inputs 7 6
Inputs channels with high-resolution capability (HRCAP) Yes (2, eCAP6 and eCAP7) No
Event filter reset bit Yes (ECCTL2.CTRFILTRESET) No
Modulo counter (4 bit sequencer) status bits Yes (ECCTL2.MODCNTRSTS) No
DMA Event generation Yes (ECCTL2.DMAEVTSEL) No
EALLOW protection for registers Yes No
Input select for eCAP Input for each eCAP module can be selected out of 128 input source including 16 outputs of INPUT XBAR. Input selection is done by ECCCTLx.INPUTSEL Fixed input from INPUT XBAR for each eCAP module
SYNC Scheme Generic Any-To-Any Scheme Daisy Chain
Configuration register for SYNC Select ECAPSYNCINSELECT SYNCSELECT

Even though there are some enhancements to the existing feature of the eCAP module, like different input selection logic and EALLOW protection for configuration register, care has to be taken to avoid breaking the compatibility with F2837x code.

The Following implementation has been done to avoid this:

  • Default value of ECCTLx.INPUTSELECT is 0x7F (127) and that selects the same input source as on F2837x.
  • ECAPTYPE.TYPE configuration bit is added to enable EALLOW protection for eCAP registers. By default, EALLOW protection is not enabled. You can set ECAPTYPE.TYPE = 1 to enable EALLOW protection.

The new SYNC scheme breaks the code compatibility with F2837x. Therefore, you need to modify the respective code while migrating between the F2837x and F2838x devices. For more details on the eCAP module and new SYNC scheme, see the TMS320F2838x Microcontrollers Technical Reference Manual.