SPRACQ1 May   2020 TMS320F28374D , TMS320F28374S , TMS320F28375D , TMS320F28375S , TMS320F28376D , TMS320F28376S , TMS320F28377D , TMS320F28377S , TMS320F28379D , TMS320F28379S , TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

 

  1.   Migration Between TMS320F2837x and TMS320F2838x
    1.     Trademarks
    2. 1 Feature Differences Between F2837x and F2838x
      1. 1.1 F2837x and F2838x Feature Comparison
    3. 2 PCB Hardware Changes
      1. 2.1 VDD Pin
      2. 2.2 VREGENZ Pin
      3. 2.3 Analog Pin Assignment
      4. 2.4 GPIO Pin Assignment
      5. 2.5 controlCARD
    4. 3 Feature Differences for System Consideration
      1. 3.1 New Features in F2838x Device
        1. 3.1.1  Fast Integer Division (FINTDIV)
        2. 3.1.2  VCRC Unit
        3. 3.1.3  EtherCAT Slave Controller (ESC)
        4. 3.1.4  Background CRC (BGCRC)
        5. 3.1.5  Diagnostic Features (PBIST/HWBIST)
        6. 3.1.6  Power Management Bus Module (PMBus)
        7. 3.1.7  Fast Serial Interface (FSI)
        8. 3.1.8  Embedded Real-time Analysis and Diagnostic (ERAD)
        9. 3.1.9  Dual-Clock Comparator (DCC)
        10. 3.1.10 Connectivity Manager (CM)
      2. 3.2 Features Differences/Enhancements in F2838x
        1. 3.2.1 System
          1. 3.2.1.1 Reset
          2. 3.2.1.2 Clocking
            1. 3.2.1.2.1 PLL
            2. 3.2.1.2.2 X1CNT
            3. 3.2.1.2.3 XCLKOUT
          3. 3.2.1.3 Pie Channel Mapping and Interrupt
            1. 3.2.1.3.1 SYS_ERR Interrupt
          4. 3.2.1.4 ERRORSTS Pin
        2. 3.2.2 Watchdog and NMI Watchdog
        3. 3.2.3 Memory
          1. 3.2.3.1 Internal SRAM/ROM
          2. 3.2.3.2 Flash
        4. 3.2.4 Dual Code Security Module (DCSM)
        5. 3.2.5 ROM Code and Peripheral Booting
        6. 3.2.6 External Memory Interface (EMIF)
        7. 3.2.7 Communication Modules
        8. 3.2.8 Control Modules
          1. 3.2.8.1 Enhanced Pulse Width Modulator (ePWM) and ePWM Sync Scheme
          2. 3.2.8.2 Enhanced Capture (eCAP)
          3. 3.2.8.3 Enhanced Quadrature Encoder Pulse (eQEP)
          4. 3.2.8.4 Sigma Delta Filter Module (SDFM)
        9. 3.2.9 Analog Modules
      3. 3.3 Other Device Changes
        1. 3.3.1 Bus Architecture
          1. 3.3.1.1 CLA and DMA Access
        2. 3.3.2 Control Law Accelerator (CLA)
        3. 3.3.3 Direct Memory Access (DMA)
      4. 3.4 Power Management
        1. 3.4.1 LDO/VREG
        2. 3.4.2 POR/BOR
      5. 3.5 Power Consumption
      6. 3.6 GPIO
        1. 3.6.1 GPIO Multiplexing Diagram
    5. 4 Application Code Migration From F2837x to F2838x
      1. 4.1 C2000Ware Driverlib Files
      2. 4.2 C2000Ware Header Files
      3. 4.3 Linker command Files
      4. 4.4 Minimum Compiler Version Requirement
      5. 4.5 EABI Support
        1. 4.5.1 Flash API
        2. 4.5.2 NoINIT Struct Fix (linker command)
        3. 4.5.3 Pre-Compiled Libraries
    6. 5 References

Pie Channel Mapping and Interrupt

Pie channel mapping between F2837x and F2838x is different due to the peripheral module changes between these devices.

Table 6 summarizes the common and unique pie channels on these two devices.

Table 5. Pie Channel Legend

Color Description
Pie channel common for both devices
Pie channel applicable only for F2837x
F2837x INT has been replaced with new INT on F2838x
Pie channel applicable only for F2838x

Table 6. PIE Channel Mapping

INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 INTx.9 INTx.10 INTx.11 INTx.12 INTx.13 INTx.14 INTx.15 INTx.16
INT1.y ADCA1 ADCB1 ADCC1 XINT1 XINT2 ADCD1 TIMER0 WAKE/
WDINT
I2CA SYS_
ERR
ECAT
SYNC0
(CPU1 only)
ECAT
INTn
(CPU1 only)
CIPC0 CIPC1 CIPC2 CIPC3
INT2.y EPWM1_
TZ
EPWM2_
TZ
EPWM3_
TZ
EPWM4_
TZ
EPWM5_
TZ
EPWM6_
TZ
EPWM7_
TZ
EPWM8_
TZ
EPWM9_
TZ
EPWM10_
TZ
EPWM11_
TZ
EPWM12_
TZ
EPWM13_
TZ
EPWM14_
TZ
EPWM15_
TZ
EPWM16_
TZ
INT3.y EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 EPWM7 EPWM8 EPWM9 EPWM10 EPWM11 EPWM12 EPWM13 EPWM14 EPWM15 EPWM16
INT4.y ECAP1 ECAP2 ECAP3 ECAP4 ECAP5 ECAP6 ECAP7 - (1) FSITXA_
INT1
FSITXA_
INT2
FSITXB_
INT1
FSITXB_
INT2
FSIRXA_
INT1
FSIRXA_
INT2
FSIRXB_
INT1
FSIRXB_
INT2
INT5.y EQEP1 EQEP2 EQEP3 - CLB1 CLB2 CLB3 CLB4 SDFM1 SDFM2 ECAT
RSTINTn
(CPU1 only)
ECAT
SYNC1
(CPU1 only)
SDFM1
DR1
SDFM1
DR2
SDFM1
DR3
SDFM1
DR4
INT6.y SPIA_RX SPIA_TX SPIB_RX SPIB_TX MCBSPA_
RX
MCBSPA_
TX
MCBSPB_
RX
MCBSPB_
TX
SPIC_RX SPIC_TX SPID_RX SPID_TX SDFM2
DR1
SDFM2
DR2
SDFM2
DR3
SDFM2
DR4
INT7.y DMA_CH1 DMA_CH2 DMA_CH3 DMA_CH4 DMA_CH5 DMA_CH6 - - FSIRXC_
INT1
FSIRXC_
INT2
FSIRXD_
INT1
FSIRXD_
INT2
FSIRXE_
INT1
FSIRXE_
INT2
FSIRXF_
INT1
FSIRXF_
INT2
INT8.y I2CA I2CA_
FIFO
I2CB I2CB_
FIFO
SCIC_RX SCIC_TX SCID_RX SCID_TX FSIRXG_
INT1
FSIRXG_
INT2
FSIRXH_
INT1
FSIRXH_
INT2
CLB5 CLB6 CLB7 CLB8
INT9.y SCIA_RX SCIA_TX SCIB_RX SCIB_TX CANA_0 CANA_1 CANB_0 CANB_1 MCANSS_
INT0
(CPU1 only)
MCANSS_
INT1
(CPU1 only)
MCANSS_
ECC_
CORR_
PUL_INT
(CPU1 only)
MCANSS_
WAKE_
AND_TS_
PLS_INT
(CPU1 only)
PMBUSA CM_
STATUS
(CPU1 only)
USBA
(CPU1 only)
-
INT10.y ADCA_
EVT
ADCA2 ADCA3 ADCA4 ADCB_
EVT
ADCB2 ADCB3 ADCB4 ADCC_EVT ADCC2 ADCC3 ADCC4 ADCD_EVT ADCD2 ADCD3 ADCD4
INT11.y CLA1_1 CLA1_2 CLA1_3 CLA1_4 CLA1_5 CLA1_6 CLA1_7 CLA1_8 CMTOCPUx
IPCINTR0
CMTOCPUx
IPCINTR1
CMTOCPUx
IPCINTR2
CMTOCPUx
IPCINTR3
CMTOCPUx
IPCINTR4
CMTOCPUx
IPCINTR5
CMTOCPUx
IPCINTR6
CMTOCPUx
IPCINTR7
INT12.y XINT3 XINT4 XINT5 MPOST FMC.
DONE
VCU FPU
OVER
FLOW
FPU
UNDER
FLOW
EMIF_
ERROR
ECAP6
INT2
ECAP7
INT2
RAM_ACCE
SS_VIOLAT
ION
CPUxCRC_
INT
CLA1CRC_
INT
CLA
OVER
FLOW
CLA
UNDER
FLOW
  1. Cells marked "-" are Reserved. CPUx is CPU1 for CPU1 PIE and CPU2 for CPU2 PIE.