SPRAD00
December 2021
TDA4VM
Trademarks
1
Introduction
2
Jacinto 7 Display Subsystem Overview
2.1
Video (Input) Pipelines
2.2
Writeback Pipeline
2.3
Overlay Manager
2.4
Output Processing
2.5
Output Display Interfaces
2.5.1
Embedded Display Port (eDP)
2.5.2
MIPI Display Serial Interface (DSI)
2.5.3
Display Parallel Interface (DPI)
2.6
Safety Support
3
Display Subsystem Use-case Examples
3.1
3-Display Configuration
4
TDA4VM/DRA829V Hardware Display Support
5
Display Subsystem Software Architecture
5.1
Linux DSS Architecture
5.2
QNX Software Architecture
5.3
RTOS-Based DSS Support
6
References
2.5.2
MIPI Display Serial Interface (DSI)
Compliance with MIPI DSI v1.3.1 protocol specification and previous specifications
Programmable display resolutions with maximum clock rate not exceeding the total available bandwidth over 4MPix @60fps
Supporting resolutions up to 2560x1440 @60fps (2.5K)
The MIPI DSI (Physical Layer) D-PHY module supports:
Compliance with MIPI D-PHY 1.2 physical layer interface specification and features
1, 2 or 4 data lanes, in addition to clock signaling
Maximum data rate up to 2.5 Gbps per data lane
It supports up to 4 x 2.5 Gbps D-PHY data lanes in a single-link configuration and handles the byte lane mapping per use case (1, 2, 3, or 4-lanes)