SPRAD59 October   2023 TMS320F280039

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between DCAN and MCAN
  6. 3 Module Initialization
    1. 3.1 DCAN Initialization
    2. 3.2 MCAN Initialization
    3. 3.3 Initialization sequence
    4. 3.4 Code Snippets for Module Initialization
  7. 4 Bit Timing Configuration
  8. 5 Message RAM Configuration
  9. 6 Interrupt handling
    1. 6.1 MCAN Interrupt Sources
    2. 6.2 DCAN Interrupt Handling
    3. 6.3 MCAN Interrupt Handling
  10. 7 Transmitting data
    1. 7.1 Basic Transmission Process
      1. 7.1.1 Transmission with DCAN
      2. 7.1.2 Transmission with MCAN
    2. 7.2 MCAN Vs DCAN Transmit Procedural Differences
    3. 7.3 MCAN Transmit Concepts
      1. 7.3.1 Tx Event FIFO
  11. 8 Receiving Data
    1. 8.1 Introduction to Reception
    2. 8.2 Basic Reception Process
      1. 8.2.1 DCAN Reception
      2. 8.2.2 MCAN Reception
    3. 8.3 Filter Elements
      1. 8.3.1 Filter Element Structure
    4. 8.4 Rx Buffer
      1. 8.4.1 Receiving in Rx Buffer
    5. 8.5 Rx FIFO
      1. 8.5.1 Receiving in Rx FIFO
    6. 8.6 Receiving High Priority Messages
  12. 9 Avoiding network errors
  13. 10References

8.5 Rx FIFO

Rx FIFO Elements are structurally identical to Rx Buffer Elements, and are also stored in the Message RAM. The module has two Rx FIFOs (Rx FIFO 0 and Rx FIFO 1) which can be individually configured to have up to 64 elements. The primary difference between Rx Buffer Elements and Rx FIFO Elements is in how the module accesses them.

The behaviour of the Rx FIFOs is determined by the Put and Get indices. These indices are maintained by the module in specific registers (MCAN_RXFxS). The Put index refers to the FIFO Element number where a newly received frame needs to be stored in the Message RAM. The Get index refers to the FIFO Element number from where the application needs to read the data from the Message RAM.

As a result of this structure, it is not necessary for the application to retrieve the data from a Rx Buffer Element each time a frame is received and clear the corresponding New Data Flag to receive the next matching frame in the same Rx Buffer Element. Instead, the application can read multiple received frames in one go.

The starting address for each FIFO section is stored in MCAN_RXFxC.FxSA register and the subsequent regions within this section are calculated based on the Put and Get indices by the module.

The Put index is incremented (automatically by the module) every time a new message is received into the FIFO, whereas, the Get index needs to be incremented by the application every time a message is read by the application. The Fill level of the FIFO, which translates to the number of messages in the FIFO to be read by the application, is determined by (Put Index - Get Index).

There are two modes for FIFOs which are differentiated on the basis of their behaviour when a new message is received when the FIFO is full. First is FIFO blocking mode, which means that when the Rx FIFO is full, no messages are stored in the Rx FIFO, unless at least one of the messages currently stored has been read by the application. In case a new message is received, there is an interrupt flag (MCAN_IR.RXFxL) that is set denoting a lost message. Second is the FIFO overwrite mode, which means that when the Rx FIFO is full, the next accepted message overwrites the oldest FIFO message.

The Rx FIFO mode is set during initialization as part of the Message RAM configuration.