SPRADI2 March   2025 AM62L

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary
  16. 14Revision History

9 SerDes Interfaces

The package BGA ball map is also arranged to support routing the higher priority interfaces first. Thus, the SerDes DSI interfaces are located towards the outer two rings. The differential receive pair should be routed away from the SoC on the top layer, leaving a region without vias which blocks inner rows from escaping. The lanes located on inner BGA rows require vias to escape as a differential pair on the bottom or on an interior layer. The VCA facilitates this for inner rows. See Figure 9-1 for an example of the escape of the SerDes signals on the AM62Lx board on the top layer. Wide traces can limit the signal loss but could violate the impedance requirements. For more detailed information on routing SerDes signals, refer to the document on High-Speed Interface Layout Guidelines.

Serdes DSI Escapes for TOP Layer Figure 9-1 Serdes DSI Escapes for TOP Layer