SPRADI2 March   2025 AM62L

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary
  16. 14Revision History

1 Introduction

AM62Lx is an extension of the low-power, low-cost Sitara Industrial/Auto grade family of processors. AM62Lx is based on the Cortex-A53 microprocessor, alongwith extensive peripheral and networking options for a variety of embedded applications. AM62Lx is available in a 11.9mm x 11.9mm VCA package with a mix of 0.5mm ball pitch. The package BGA design is built leveraging TI Via Channel Array Technology (VCA) technology, which enables package miniaturization while still utilizing low cost PCB routing rules. Via Channel Array (VCA) is built with careful considerations on escape routing to avoid costly High-Density Interconnect (HDI) and expensive Via technologies. This document is intended to provide a reference for escape routing on the AM62Lx device. Care must be taken to route signals with special requirements such as DDR, high speed interfaces. Refer to the High-Speed Interface Layout Guidelines and DDR Routing Guidelines for more details. Details on Power Delivery Network are provided in AM62Lx PDN Application note and any routing and layout requirements specified in those documents supersede the generic requirements provided here.