SPRADI2 March   2025 AM62L

 

  1.   1
  2.   Trademarks
  3. 1 Introduction
  4. 2 Via Channel Arrays
  5. 3 Width/Spacing Proposal for Escapes
  6. 4 Stackup
  7. 5 Via Sharing
  8. 6 Floorplan Component Placement
  9. 7 Critical Interfaces Impact Placement
  10. 8 Routing Priority
  11. 9 SerDes Interfaces
  12. 10DDR Interfaces
  13. 11Power Decoupling
  14. 12Route Lowest Priority Interfaces Last
  15. 13Summary
  16. 14Revision History

3 Width/Spacing Proposal for Escapes

The AM62Lx via channel array solution has been designed to support the following. The AM62Lx package supports a similar feature set as several other competition solutions with approximately 15% smaller package area and ~10% wider line width. This solution thus reduces PCB foot print and uses lower cost PCB rules, enabling compact and low-cost systems.

Table 3-1 Width/Spacing Proposal for Escapes
PCB Feature PCB Routing Requirements
Minimum via pad diameter 18 mils
Via hole size 8 mils
Minimum trace width/spacing required in the BGA break out

External Layers: 3.2 mil/3.2 mil

Internal Layers: 3.7 mil/4 mil
Number of layers used for escape 4
BGA land pad size 10 mils
Package Size 11.9mm x 11.9mm, 0.5mm pitch w/ VCA
PCB layers (signal routing, total) recommended 2, 6 (Excluding signal escapes on top layer)
Solder resist clearance 12 mils (1 mil annular)