SPRADK1 September   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62L , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Spread-Spectrum Clocking
    1. 1.1 SSC Modulation Rate
    2. 1.2 SSC Modulation Depth
    3. 1.3 SSC Spread Type
    4. 1.4 SSC Modulation Profile
  5. 2PLL SSC Implementation Details
    1. 2.1 PLL SSC Configuration Registers
    2. 2.2 PLL SSC Implementation Sequence With DSS PLL17 on AM62Px
  6. 3SSC Conclusion and Considerations

2.2 PLL SSC Implementation Sequence With DSS PLL17 on AM62Px

The SSC manual implementation sequence described below needs to be done after the full PLL sequence (as defined by the API firmware) occurs and the PLL is locked. The SSC registers described in this document no longer need to be reconfigured manually once a standard SSC software interface is put in place with the SDK11.2 release, which is anticipated to happen at the end of 2025.

  1. To enable fractional divide mode since spectrum spreading is not allowed in integer mode, enable the delta-sigma modulator by setting PLL17_CTRL[1] DSM_EN to 1’b1 and enable the fractional noise canceling DAC (if not already enabled) by setting PLL17_CTRL[0] DAC_EN to 1’b1.
    • Set 0x691020 to 0x00018013
  2. Enable spread-spectrum modulation by setting PLL17_SS_CTRL[31] BYPASS_EN to 1’b0
    • Set 0x691040 to 0x00000000
  3. Set the spread type by setting PLL17_SS_CTRL[4] DOWNSPREAD_EN to 1’b0 for center spread or 1’b1 if down spread
    1. If down spread, set 0x691040 to 0x00000010
    2. If center spread, set 0x691040 to 0x00000000
  4. Set the modulation rate by setting PLL17_SS_SPREAD[19:16] MOD_DIV. 1’h6 corresponds to a modulation rate of 32.6kHz and 1’h2 corresponds to a modulation rate of 97.7kHz.
  5. Set the modulation depth by setting PLL17_SS_SPREAD[4:0] SPREAD. 1’h1F corresponds to a modulation depth of 3.1% and 1’h01 corresponds to a modulation depth of 0.1%.
    1. If mod rate of 32.6kHz and mod depth of 3.1%, set 0x691044 to 0x0006001F
    2. If mod rate of 97.7kHz and mod depth of 0.1%, set 0x691044 0x00020001

CAUTION: When using center spread, maintain these two things:
  1. Target display is capable of communicating with the SoC at the higher and lower peak modulation frequencies.
  2. The highest frequency of the clock after SSC must still be less than 165MHz. The overshoot of 20% on the modulated depth must also be factored in while computing the highest possible frequency.