SPRADK1 September   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62L , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Spread-Spectrum Clocking
    1. 1.1 SSC Modulation Rate
    2. 1.2 SSC Modulation Depth
    3. 1.3 SSC Spread Type
    4. 1.4 SSC Modulation Profile
  5. 2PLL SSC Implementation Details
    1. 2.1 PLL SSC Configuration Registers
    2. 2.2 PLL SSC Implementation Sequence With DSS PLL17 on AM62Px
  6. 3SSC Conclusion and Considerations

2 PLL SSC Implementation Details

The PLL reference clock frequency, fREF, undergoes an input predivider of REFDIV. This stage transforms high-speed signals into lower-frequency versions for processing. Next, a feedback multiplier (FB_DIV_INT) acts as a Voltage-Controlled Oscillator (VCO) and filter on the transformed signal. The filtered output feeds back to fine-tune performance. Finally, a post-divider, configured as HSDIV + 1, further decreases the signal frequency before being delivered by the PLL clock generator. The clock output frequency is calculated as
fc = (fREF / REFDIV) × FB_DIV_INT / (HSDIV + 1). SSC is accomplished by varying FB_DIV_INT in small steps following a triangular pattern.

For the display parallel interface (DPI), the PLL used by the display subsystem (DSS) is commonly multiplexed to PLL17 by default for AM62x, AM62Ax, AM62Px, and AM62Lx. However, PLL16 or PLL18 can also be used for DPI. The pixel clock frequency for DPI coming from the DSS PLL (that is, PLL17) must not exceed 165MHz.

Table 2-1 SSC Supported Configurations
Parameter MIN MAX Unit
Modulation depth 0.1 3.1 %
Spread type Both center spread and down spread are supported
Modulation rate 32 fCLKSSCG / 200 kHz
CAUTION: For DPI applications with SSC, only the DSS PLL allocated for DPI (PLL16, PLL17, or PLL18) is approved to be changed by customers. Use of other PLLs is neither approved nor recommended.