SPRADK1 September   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62L , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Spread-Spectrum Clocking
    1. 1.1 SSC Modulation Rate
    2. 1.2 SSC Modulation Depth
    3. 1.3 SSC Spread Type
    4. 1.4 SSC Modulation Profile
  5. 2PLL SSC Implementation Details
    1. 2.1 PLL SSC Configuration Registers
    2. 2.2 PLL SSC Implementation Sequence With DSS PLL17 on AM62Px
  6. 3SSC Conclusion and Considerations

2.1 PLL SSC Configuration Registers

Table 2-2 describes the registers involved to configure SSC for PLL17, which is the DSS PLL commonly used for DPI.

Table 2-2 SSC Related Register Fields
Register Name Physical Address Offset Bit Field Information
Bit No. Name Description
PLL17_CTRL 0x11020 1 DSM_EN Delta-sigma modulator enable
1'b0: Delta-sigma modulator disabled (integer divide mode)
1'b1: Delta-sigma modulator enabled (fractional divide mode)
0 DAC_EN Fractional noise canceling DAC enable
1'b0: Fractional noise canceling DAC is disabled
1'b1: Fractional noise canceling DAC is enabled
PLL17_SS_CTRL 0x11040 31 BYPASS_EN Bypass the SS modulator
1'b0: Spread-spectrum modulation (SSMOD) is enabled
1'b1: SSMOD is bypassed
4 DOWNSPREAD_EN Center or down spread clock variance select
1'b0: Center spread
1'b1: Down spread
PLL17_SS_SPREAD 0x11044 19:16 MOD_DIV Input clock divider. This divider sets the modulation frequency. Supports divide values of 1–63.
fmod = fCLKSSCG / (128 × MOD_DIV).
1'h6: 32.6kHz if fCLKSSCG = 25MHz
1'h5: 39.1kHz if fCLKSSCG = 25MHz
1'h4: 48.8kHz if fCLKSSCG = 25MHz
1'h3: 65.1kHz if fCLKSSCG = 25MHz
1'h2: 97.7kHz if fCLKSSCG = 25MHz
4:0 SPREAD Sets the spread modulation depth
5'b00001: 0.1%
5'b01010: 1%
5'b10100: 2%
5'b11001: 2.5%
5'b11111: 3.1%