SPRADK1 September   2025 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP , AM62A1-Q1 , AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62L , AM62P , AM62P-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Spread-Spectrum Clocking
    1. 1.1 SSC Modulation Rate
    2. 1.2 SSC Modulation Depth
    3. 1.3 SSC Spread Type
    4. 1.4 SSC Modulation Profile
  5. 2PLL SSC Implementation Details
    1. 2.1 PLL SSC Configuration Registers
    2. 2.2 PLL SSC Implementation Sequence With DSS PLL17 on AM62Px
  6. 3SSC Conclusion and Considerations

1.1 SSC Modulation Rate

The modulation period is the time required to cycle the clock nominal frequency from an initial value through all the different values along the modulation profile and back to the initial value. The modulation rate is the inverse of the period.

  1. The modulation rate is controlled by the CLKSSCG, the 128-point internal wave table, and the divide value MOD_DIV as fmod = fCLKSSCG / (128 × MOD_DIV).
  2. fCLKSSCG = fREF / REFDIV. With fractional-N mode set for AM62x, AM62Ax, AM62Px, and AM62Lx:
    REFDIV = 1. This means in this case fCLKSSCG = fREF, where fREF is the PLL reference clock
    (for example, fREF = 25MHz).
  3. For modulation fidelity, which is determined by the PLL bandwidth, and to avoid interference with audio applications, the modulation frequency is typically set above 32kHz and below fCLKSSCG / 200. For example, the maximum modulation frequency if a PLL reference clock frequency of 25MHz is used, is 125kHz.