SPRADK2A November   2024  – October 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. Introduction
  5. Supplemental Online Information
  6. SSU Overview
  7. Key Concept Definitions
  8. Safety and Security Goals
  9. System Design
  10. Configuring the SSU
    1. 7.1 Flash SECCFG Region
    2. 7.2 SSU Development Life Cycle
    3. 7.3 Using the SysConfig Tool
      1. 7.3.1 Enabling System Security Configuration
      2. 7.3.2 Configuring Application Modules
      3. 7.3.3 Configuring Special Modules
        1. 7.3.3.1 LINK2 Configuration
        2. 7.3.3.2 LINK1 Configuration
        3. 7.3.3.3 Common Code Link Configuration
      4. 7.3.4 Defining Sandboxes
      5. 7.3.5 Adding Shared Memory
  11. Debug Authorization
    1. 8.1 Password-Based Unlock
  12. Debugging the SSU
    1. 9.1 Debugging Build Errors
    2. 9.2 Debugging Runtime Errors
  13. 10SSU Frequently Asked Questions (FAQ)
  14. 11Summary
  15. 12References
  16. 13Revision History

LINK2 Configuration

LINK2 is the most secure LINK on each CPU. LINK2 has elevated privileges, including the ability to access secure CPU registers and perform supervisory tasks. In most cases, RTOS layer functions are placed in LINK2. CPU1.LINK2 in particular has special device-wide elevated privileges, including:

  • Ability to write to device configuration registers
  • Ability to write to certain SSU registers
  • Ability to configure the RTDMA, including MPU configuration

Place all code and data sections that are responsible for performing initial system configuration and board configuration and running operating system functions in LINK2. Table 7-1 describes the peripheral registers that are mandatory for LINK2 and why those registers are mandatory.

Table 7-1 Mandatory Peripheral Access Protection for LINK2
Peripheral Register Base Reason
CPU_SYS_REGS CPU system registers
PER_CFG_REGS_WD_REGS Setup watchdog registers
CPUTIMER2_REGS CPU timer 2 registers for the driver porting layer (DPL)
DCC1_REGS Clock monitor
ERR_AGG_REGS Error/NMI Handling
ESM_CPU1_REGS Error/NMI Handling
ESM_CPU2_REGS Error/NMI Handling
ESM_CPU3_REGS Error/NMI Handling
ESM_SYS_REGS Error/NMI Handling
ESM_SAFETY_AGG_REGS Error/NMI Handling
 LINK2 Configuration
                    Example Figure 7-4 LINK2 Configuration Example