SPRADK2A November   2024  – October 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Supplemental Online Information
  6. 3 SSU Overview
  7. 4 Key Concept Definitions
  8. 5 Safety and Security Goals
  9. 6 System Design
  10. 7 Configuring the SSU
    1. 7.1 Flash SECCFG Region
    2. 7.2 SSU Development Life Cycle
    3. 7.3 Using the SysConfig Tool
      1. 7.3.1 Enabling System Security Configuration
      2. 7.3.2 Configuring Application Modules
      3. 7.3.3 Configuring Special Modules
        1. 7.3.3.1 LINK2 Configuration
        2. 7.3.3.2 LINK1 Configuration
        3. 7.3.3.3 Common Code Link Configuration
      4. 7.3.4 Defining Sandboxes
      5. 7.3.5 Adding Shared Memory
  11. 8 Debug Authorization
    1. 8.1 Password-Based Unlock
  12. 9 Debugging the SSU
    1. 9.1 Debugging Build Errors
    2. 9.2 Debugging Runtime Errors
  13. 10SSU Frequently Asked Questions (FAQ)
  14. 11Summary
  15. 12References
  16. 13Revision History

7.3.3.2 LINK1 Configuration

CPU1.LINK1 is primarily used for bootloaders, and has extra hard-coded privileges to support bootloader functions, such as the ability to write to certain system configuration registers. LINK1 can also be used as a conventional user LINK; however, adding non-bootloader-related code and data to LINK1 is not recommended except as a last resort when all other LINKs are already in use.

When any peripheral boot mode is configured in the Boot Settings group, SysConfig automatically configures LINK1 to have access to the respective peripherals required for that boot mode to function, for example, CAN, UART, or SPI. These peripherals are automatically added to the LINK1 module by SysConfig, in addition to certain peripherals that are always required for device boot, such as IPC and the HSM mailbox. Table 7-2 describes the full list of mandatory peripherals required for LINK1 as part of device boot.

Table 7-2 Mandatory Peripheral Access Protection for LINK1
Peripheral Register Base Reason
PER_CFG_REGS_WD_REGS Setup for watchdog registers
IPC_CPU1_SEND_REGS_HSM_CH0 Handshake with HSM during device authentication
IPC_CPU1_SEND_REGS_HSM_CH1 Handshake with HSM during device authentication
HSM_MAILBOX HSM Mailbox for IPC
GPIO_DATA_REGS Boot mode selection and error status pin configuration
MCANA_MSGRAM Peripheral boot mode
MCANA_REGS Peripheral boot mode
UARTA_REGS Peripheral boot mode
DCC1_REGS Clock monitor
ERR_AGG_REGS Error/NMI Handling
ESM_CPU1_REGS Error/NMI Handling