1 Introduction

Current indicators suggest that traditional MCUs with embedded flash on the same die, as shown in Figure 1-1, will not scale beyond a 22 nm technology node due to high-voltage circuits required for programming and erasing flash. Flash-based processes are also costly due to large number of masks required to integrate embedded flash on MCU/SOC die using deep sub-micron digital CMOS technology. Thus, these MCUs will only work for older process nodes (such as 28nm, 40nm, 65nm…).

There are also alternate new NVM technologies coming up such as MRAM, RRAM, and so forth, but even these are not yet ready for high-reliability applications such as automotive.

High-performance MCUs, as shown in High Performance MCU, use an external Flash Memory part and typically download the entire image to SRAM during boot time. These MCUs, depending on their processing and power needs based on application they are addressing, work across process nodes (for example, down to newer process nodes such as 3/5nm or custom nodes like 45nm), where flash technology is not available. Also, having a separate flash part is cheaper due to the flash only process node. Most common disadvantage of these MCUs is the cost due to large SRAM size (>= Application SW Image Size) and large boot/startup time.