SPRADP7A February   2025  – March 2025 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM67A , TDA4AEN-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Building Blocks of an RGB-IR Vision Pipeline
    1. 2.1 CSI Receiver
    2. 2.2 Image Signal Processor
    3. 2.3 Video Processing Unit
    4. 2.4 TI Deep Learning Acceleration
    5. 2.5 GStreamer and TIOVX Frameworks
  6. 3Performance Considerations and Benchmarking Tools
  7. 4Reference Design
    1. 4.1 Camera Module
    2. 4.2 Sensor Driver
    3. 4.3 CSI-2 Rx Driver
    4. 4.4 Image Processing
    5. 4.5 Deep Learning for Driver and Occupancy Monitoring
    6. 4.6 Reference Code and Applications
  8. 5Application Examples and Benchmarking
    1. 5.1 Application 1: Single-stream Capture and Visualization with GST
    2. 5.2 Application 2: Dual-stream Capture and Visualization with GST and TIOVX Frameworks
    3. 5.3 Application 3: Representative OMS-DMS + Video Telephony Pipeline in GStreamer
  9. 6Summary
  10. 7References
  11. 8Revision History

Application 1: Single-stream Capture and Visualization with GST

This is a simple example of streaming from the camera to a display and visualizing the RGB data. This example demonstrates how the performance metrics listed in Section 3 were benchmarked. The components of the GStreamer pipeline of this example are shown below.

 RGB Stream Capture And Display
                    With Gstreamer Figure 5-1 RGB Stream Capture And Display With Gstreamer

The corresponding GST command can be found in the GitHub repo [6]. To benchmark the performance metrics, this command was run in one terminal console and the perf_stats tool [5] was run in another terminal console simultaneously.

  • Pipeline throughput (fps) was printed out in the first console, as shown in Figure 5-2. The throughput was also shown on the display.
  • CPU load, HWA load, and DDR utilization were printed out in the second console and shown on the display as well. These performance metrics were constantly updated while the GST command was running. Figure 5-3 shows a screen capture of a single update.
  • After stopping the GST pipeline, run “/opt/edgeai-gst-apps/scripts/gst_tracers/parse_gst_tracers.py /run/trace.log” to generate the latency measurements of each element in the pipeline, as shown in Figure 5-4. The latencies for tiovxisp0 (VISS), tiovxldc0 (LDC), and tiovxmultiscaler0 (MSC) shown in the figure are as expected:
    • For VISS and LDC, latency is approximately 5MPixel/375MHz + overhead ≃ 14-15msec, where 375MHz is the ISP(VPAC) operating clock frequency.
    • For MSC, the YUV data can be processed simultaneously or separately. When processed separately (the default configuration), luma (Y) plane latency is about 14-15 msec, the same as VISS and LDC, while chroma (UV) plane latency is about half of luma plane latency, or 7 msec. Then total latency for MSC is about 21 msec. This latency can be reduced to 14 msec by configuring the MSC to process both planes simultaneously.
 Pipeline Throughput of Single
                    Stream Capture and Visualization Figure 5-2 Pipeline Throughput of Single Stream Capture and Visualization
 CPU, HWA, and DDR Load of
                    Single Stream Capture and Visualization Figure 5-3 CPU, HWA, and DDR Load of Single Stream Capture and Visualization
 Pipeline Element Latencies of
                    Single Stream Capture and Visualization Figure 5-4 Pipeline Element Latencies of Single Stream Capture and Visualization