SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

2.5.1.4 Task Manager Configuration

Set the task manager to general purpose mode by configuring the TASKS_MGR_MODE bit field = 0x2 in TASKS_MGR_GLOBAL_CFG register (0x3002A000), enable task 2 sub task 1 by setting TS2_EN_S1 bit field = 0x1 and enable task 2 sub task 4 by setting TS2_EN_S4 bit field = 0x1.

Write the address of the TS2_S1 (CMP0 task) that has to be executed when a CMP0 event occurs to the TASKS_MGR_TS2_PC_S1 register (0x3002A020). The CMP0 task generates the sync signal in single shot mode. Write TS2_GEN_S1_MX bit field = 16 in TASKS_MGR_TS2_GEN_CFG1 register (0x3002A040) to configure CMP0 event as the trigger for executing the TS2_S1 task (CMP0 task).

So, the compare 0 event of IEP is configured to reset IEP timer with 62.5us cycle time and also to hit the task 0 to generate the SYNC0 pulse for synchronization. The SYNC0 activation time is triggered by IEP compare 1 event. The SYNC0 pulse generation mode is set to single-shot mode and pulse width set to 50ns. During the task 0, the SYNC0 pulse is disabled then enabled.

Write the address of the TS2_S4 (INTC task) that has to be executed when an FSI_RX interrupt event occurs to the TASKS_MGR_TS2_PC_S4 register (0x3002A02C). The INTC can generate the event to hit task 1 once the FSI RX buffer is filled up. During the task 1, the PRU firmware can move the position data received from remote device 2 to the tightly coupled memory (TCM) of R5F core via the PRU XFR2VBUS hardware accelerator. The TX write buffer and RX read buffer of the XFR2VBUS widget are all 64 bytes deep. Write TS2_GEN_S4_MX bit field = 136 in TASKS_MGR_TS2_GEN_CFG2 register (0x3002A044) to configure INTC event as the trigger for executing the TS2_S4 task (INTC task).