SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

2.2 IEP Timer Interface

The IEP module features an industrial Ethernet timer with 16 compare events, industrial Ethernet sync generator and latch capture, industrial Ethernet watchdog timer, and a digital I/O port. The IEP functional block diagram is shown in Figure 2-1.

IEP Timer Functional Block DiagramFigure 2-1 IEP Timer Functional Block Diagram

The sync block supports the generation of two synchronization signals: SYNC0 and SYNC1 which can be directly mapped to the output for external devices to use. The signals can also be used for internal synchronization within the PRU_ICSSG. The generation modes can be configured to four operation modes: cyclic mode, single shot mode, cyclic with acknowledge mode, and single shot with acknowledge mode as Figure 2-2 shown.

PRU_ICSSG IEP SYNC0 Signal Generation ModesFigure 2-2 PRU_ICSSG IEP SYNC0 Signal Generation Modes

The time sync router (TSR) module is designed to send one sync signal to multiple recipients. This sync signal allows multiple peripherals or cores within the processor to synchronize the counters to a single main clock. TSR signals can even be routed to processor pins if the sync signal also needs to be received by a device external to the processor. The IEP latch signal is connected to the TSR output to establish a signal path from PRU GPIO to the ICSSG_IEP_Latch. [FAQ] AM64x: What is the Time Sync Router for? How do I use it? - Processors forum - Processors - TI E2E support forums is the E2E forum post link of the introduction of TSR module.

The controller can send cyclic SYNC0 according to the control loop frequency. And the device can capture the SYNC0 signal by IEP latch and capture modules then compensate the delay time and align the timestamping with the controller.

The IEP counters of both MCUs are synchronized using sync out signal, latch and IEP counter compensation register. Both MCUs are configured to operate the IEP count at the same frequency and with same increment value. In this setup of application note, the IEP clock frequency is set to 250MHz, with the default increment value of the IEP counter being 4.