SPRADQ5 March   2025 AM2612 , AM2612-Q1 , AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1 , AM263P2-Q1 , AM263P4 , AM263P4-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction of AC or Servo Drive Hot-Side Control Architecture
  5. 2PRU and FSI Implementation for Time Synchronization and Data Transmitting
    1. 2.1 Importance of Clock in Industrial Systems With MCUs
    2. 2.2 IEP Timer Interface
    3. 2.3 PRU_ICSSG Task Manger
    4. 2.4 Fast Serial Interface
    5. 2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting
      1. 2.5.1 Device 1 Configuration
        1. 2.5.1.1 Pad Configuration
        2. 2.5.1.2 Clock Source Configuration
        3. 2.5.1.3 IEP Timer Configuration
        4. 2.5.1.4 Task Manager Configuration
      2. 2.5.2 Device 2 Configuration
        1. 2.5.2.1 Pad Configuration
        2. 2.5.2.2 Clock Configuration
        3. 2.5.2.3 IEP Timer Configuration
        4. 2.5.2.4 TSR Configuration
        5. 2.5.2.5 Task Manager Configuration
  6. 3Verification
  7. 4Summary
  8. 5References

2.5 Two-Chip System Scheme for Time Synchronization and Data Transmitting

Assuming that two AM243x devices with PRU_ICSSG are used for implementation for time synchronization and data transmitting. Figure 2-5 and Figure 2-6 show the system block diagram and timing for the time synchronization and data transmitting during control cycles.

Time Synchronization and Data Transmitting Block Diagram Figure 2-5 Time Synchronization and Data Transmitting Block Diagram
Time Synchronization and Data Transmitting Timing Figure 2-6 Time Synchronization and Data Transmitting Timing