SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
This reset is a software controlled MAIN domain POR reset defined in MAIN_CTRL_MMR_CFG0_RST_CTRL and MCU_CTRL_MMR_CFG0_RST_CTRL.
This software reset will generate a MAIN domain PORz.
M4FSS processor will reset the MAIN domain, by writing to the MCU_CTRL_MMR_CFG0_RST_CTRL register.
MAIN domain processors will reset the MAIN domain, by writing to the MAIN_CTRL_MMR_CFG0_RST_CTRL register.
When the MCU domain is configured as a safety domain it must be isolated from SW_MAIN_PORz.
A reset isolation sequence for the MCU domain must be complete prior to reset propagation.
MAIN_CTRL_MMR_CFG0_RST_CTRL and MCU_CTRL_MMR_CFG0_RST_CTRL define a 4-bit field, SW_MAIN_POR[4:7], for generating a software controlled POR for the MAIN domain (SW_MAIN_PORz).
When SW_MAIN_POR [4:7] field is set to “0110”, the MAIN domain is in POR reset state (SW_MAIN_PORz = LOW).
When SW_MAIN_POR [4:7] is set to any other value, the MAIN domain is out of POR reset state (SW_MAIN_PORz = HIGH).
This bit field is reset to “1111” (Inactive State) by default.
Entire MCU domain is reset isolated.
MCU IOs are not effected.
All modules in MAIN domain are reset (including reset isolated modules).
IOs will enter High-Heating-Value (HHV) mode while this reset is active.
MAIN domain CTRLMMR boot configuration register is reset.
Device Boot Mode pins will be re-latched after this reset is de-asserted.
Device will re-boot. During boot-up, R5FSS (secondary boot loader) will poll the CTRLMMR reset status and MCU ACTIVE MAGIC WORD registers and configure MCU domain/M4FSS processor accordingly.
PORz_OUT:
This pin indicates POR status output of the MAIN domain (active LOW).
When LOW, it indicates the MAIN domain is in POR state.
When HIGH, it indicates that the MAIN domain is out of POR state.
PORz_OUT must be used to tri-state boot mode pins which are mapped on MAIN IOs so that boot modes set by external pull-up/down resistors can propagate safely into device.
The boot mode pins are latched internally on the rising edge of MAIN_PORz and are reset isolated from all other device resets.