SPRUIM2J May 2020 – May 2026 AM2431 , AM2432 , AM2434 , AM6411 , AM6412 , AM6421 , AM6422 , AM6441 , AM6442
Figure 5-155 Reset Architecture Block Diagram. This is the device reset architecture block diagram. It describes the device reset sub-modules and critical internal signal interconnections.
Figure 5-156 SoC Reset Hardware Logic Diagram. This is the reset hardware logic diagram. It describes the MAIN and MCU reset domains and processors connections as well as the available reset sources including reset pins and CTRLMMRs.
Figure 5-157 MCU Domain Reset Hardware Logic Diagram. This diagram shows the external and internal signals associated with the MCU domain resets.
Figure 5-158 MAIN Domain Reset Hardware Logic Diagram. This diagram shows the external and internal signals associated with the MAIN domain resets.